Display given number

2024-07-12 00:17:54 +08:00
parent c8a110e740
commit f391a7bfd2
78 changed files with 8031 additions and 103 deletions
--- a/PipelineProcessor.sim/sim_1/behav/xsim/test_cpu_vlog.prj
+++ b/PipelineProcessor.sim/sim_1/behav/xsim/test_cpu_vlog.prj
@@ -13,7 +13,6 @@ verilog xil_defaultlib  --include "../../../../PipelineProcessor.ip_user_files/i
 "../../../../PipelineProcessor.srcs/sources_1/new/InstFetch.v" \
 "../../../../PipelineProcessor.srcs/sources_1/new/InstructionMemory.v" \
 "../../../../PipelineProcessor.srcs/sources_1/new/MemoryAccess.v" \
-"../../../../PipelineProcessor.srcs/sources_1/new/MemoryForward.v" \
 "../../../../PipelineProcessor.srcs/sources_1/new/RegisterFile.v" \
 "../../../../PipelineProcessor.srcs/sources_1/new/WriteBack.v" \
 "../../../../PipelineProcessor.srcs/sources_1/new/CPU.v" \
--- a/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb
+++ b/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb
--- a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
+++ b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
--- a/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb
+++ b/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb