40 lines
1.0 KiB
Verilog
40 lines
1.0 KiB
Verilog
`timescale 1ns / 1ps
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module DataMemory (
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input clk,
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input reset,
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input [31:0] address,
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input write_enable,
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input [31:0] write_data,
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output reg [31:0] read_data,
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output [31:0] bcd_hardwire
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);
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parameter integer MEM_SIZE = 1024;
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parameter integer START_ADDRESS = 32'h00000000;
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reg [31:0] memory_data[MEM_SIZE + START_ADDRESS - 1:START_ADDRESS];
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assign bcd_hardwire = memory_data[START_ADDRESS+4];
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integer i;
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initial begin
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for (i = START_ADDRESS; i < MEM_SIZE + START_ADDRESS; i = i + 1) begin
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memory_data[i] <= 32'h00000000;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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for (i = START_ADDRESS; i < MEM_SIZE + START_ADDRESS; i = i + 1) begin
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memory_data[i] <= 32'h00000000;
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end
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end else begin
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if (write_enable) begin
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memory_data[address] <= write_data;
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end
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read_data <= memory_data[address];
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end
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end
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endmodule
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