61 lines
1.7 KiB
Verilog
61 lines
1.7 KiB
Verilog
`timescale 1ns / 1ps
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module RegisterFile (
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input clk,
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input reset,
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input [4:0] read_addr1,
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input [4:0] read_addr2,
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input write_enable,
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input [4:0] write_addr,
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input [31:0] write_data,
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input write_ra,
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input [4:0] write_ra_addr,
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input [31:0] write_ra_data,
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output [31:0] read_output1,
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output [31:0] read_output2
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);
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reg [31:0] registers[1:31];
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integer i;
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assign read_output1 = (read_addr1 == 5'b00000) ? 32'h00000000 :
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(read_addr1 == write_ra_addr) ? write_ra_data :
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(read_addr1 == write_addr) ? write_data : registers[read_addr1];
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assign read_output2 = (read_addr2 == 5'b00000) ? 32'h00000000 :
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(read_addr2 == write_ra_addr) ? write_ra_data :
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(read_addr2 == write_addr) ? write_data : registers[read_addr2];
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initial begin
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for (i = 1; i < 32; i = i + 1) begin
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registers[i] <= 32'h00000000;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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for (i = 1; i < 32; i = i + 1) begin
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registers[i] <= 32'h00000000;
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end
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end else begin
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if (write_addr == write_ra_addr) begin
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if (write_ra) begin
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registers[write_ra_addr] <= write_ra_data;
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end else begin
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if (write_enable) begin
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registers[write_addr] <= write_data;
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end
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end
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end else begin
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if (write_ra) begin
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registers[write_ra_addr] <= write_ra_data;
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end
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if (write_enable) begin
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registers[write_addr] <= write_data;
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end
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end
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end
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end
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endmodule
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