43 lines
1.1 KiB
Verilog
43 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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module DataMemory (
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input clk,
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input reset,
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input [31:0] address,
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input write_enable,
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input [31:0] write_data,
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output [31:0] read_data,
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output [31:0] bcd_hardwire
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);
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parameter integer MEM_SIZE_IN_WORD = 64;
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parameter integer START_ADDRESS = 32'h00000000;
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localparam integer StartAddressInWord = START_ADDRESS / 4;
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reg [31:0] memory_data[MEM_SIZE_IN_WORD + StartAddressInWord - 1 : StartAddressInWord];
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assign bcd_hardwire = memory_data[StartAddressInWord+4];
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assign read_data = memory_data[address[31:2]];
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integer i;
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initial begin
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for (i = StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1) begin
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memory_data[i] <= 32'h00000000;
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end
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end
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always @(posedge clk) begin
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if (reset) begin
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for (i = StartAddressInWord; i < MEM_SIZE_IN_WORD + StartAddressInWord; i = i + 1) begin
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memory_data[i] <= 32'h00000000;
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end
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end else begin
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if (write_enable) begin
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memory_data[address[31:2]] <= write_data;
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end
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end
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end
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endmodule
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