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Fix lw problems

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This commit is contained in:
un-lock-able
2024-07-10 18:41:29 +08:00
parent a31d499943
commit 6558f7075c
8 changed files with 24 additions and 36 deletions
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11
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/obj/xsim_2.c
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PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
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2
PipelineProcessor.srcs/sources_1/new/CPU.v
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@@ -74,7 +74,7 @@ module CPU (
wire [4:0] WB_register_write_address;
// Out of hazard control
wire [1:0] hazard_IFID_source;
wire hazard_IFID_source;
wire hazard_IDEX_source;
wire hazard_IF_need_stall;

7
PipelineProcessor.srcs/sources_1/new/DataMemory.v
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@@ -6,7 +6,7 @@ module DataMemory (
input [31:0] address,
input write_enable,
input [31:0] write_data,
output reg [31:0] read_data,
output [31:0] read_data,
output [31:0] bcd_hardwire
);
parameter integer MEM_SIZE_IN_WORD = 64;
@@ -16,7 +16,9 @@ module DataMemory (
reg [31:0] memory_data[MEM_SIZE_IN_WORD + StartAddressInWord - 1 : StartAddressInWord];
assign bcd_hardwire = memory_data[StartAddressInWord + 4];
assign bcd_hardwire = memory_data[StartAddressInWord+4];
assign read_data = memory_data[address[31:2]];
integer i;
@@ -35,7 +37,6 @@ module DataMemory (
if (write_enable) begin
memory_data[address[31:2]] <= write_data;
end
read_data <= memory_data[address[31:2]];
end
end
endmodule

9
PipelineProcessor.srcs/sources_1/new/HazardUnit.v
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@@ -3,7 +3,7 @@ module HazardUnit (
input [1:0] PC_jump,
input is_loadword,
input PC_branch,
output [1:0] IFID_source,
output IFID_source,
output IDEX_source,
output IF_need_stall
);
@@ -11,10 +11,9 @@ module HazardUnit (
wire is_jump;
assign is_jump = PC_jump == 2'b01 || PC_jump == 2'b10;
assign IFID_source = (is_loadword == 1'b1) ? 2'b10 :
(PC_branch == 1'b1 || is_jump == 1'b1) ? 2'b01 : 2'b00;
assign IFID_source = (PC_branch == 1'b1 || is_jump == 1'b1 || is_loadword == 1'b1) ? 1'b1 : 1'b0;
assign IDEX_source = (is_loadword == 1'b1 || PC_branch == 1'b1 || is_jump == 1'b1) ? 1 : 0;
assign IDEX_source = (PC_branch == 1'b1 || is_jump == 1'b1) ? 1'b1 : 1'b0;
assign IF_need_stall = (is_loadword == 1'b1) ? 1 : 0;
assign IF_need_stall = (is_loadword == 1'b1) ? 1'b1 : 1'b0;
endmodule

27
PipelineProcessor.srcs/sources_1/new/InstDecode.v
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@@ -6,7 +6,7 @@ module InstDecode (
input [31:0] prev_fetched_instruction,
input [31:0] prev_PC_plus_4,
// For hazard unit
input [1:0] IFIDSrc,
input IFIDSrc,
// From WB stage
input WB_write_enable,
input [4:0] WB_write_address,
@@ -121,24 +121,13 @@ module InstDecode (
IFID_instruction <= 32'h00000000;
IFID_PC_plus_4 <= 32'h00000000;
end else begin
case (IFIDSrc)
2'b00: begin
IFID_instruction <= prev_fetched_instruction;
IFID_PC_plus_4 <= prev_PC_plus_4;
end
2'b01: begin
IFID_instruction <= 32'h00000000;
IFID_PC_plus_4 <= 32'h00000000;
end
2'b10: begin
IFID_instruction <= IFID_instruction;
IFID_PC_plus_4 <= IFID_PC_plus_4;
end
default: begin
IFID_instruction <= 32'h00000000;
IFID_PC_plus_4 <= 32'h00000000;
end
endcase
if (IFIDSrc == 1'b1) begin
IFID_instruction <= 32'h00000000;
IFID_PC_plus_4 <= 32'h00000000;
end else begin
IFID_instruction <= prev_fetched_instruction;
IFID_PC_plus_4 <= prev_PC_plus_4;
end
end
end

2
PipelineProcessor.srcs/sources_1/new/MemoryAccess.v
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@@ -53,7 +53,7 @@ module MemoryAccess (
assign data_memory_address = MEM_ALU_result;
assign data_memory_write_data = (MEM_write_data_source == 1'b0) ?
MEM_memory_write_data : WB_forwarded_data;
assign read_data = data_memory_read_data;
assign memory_read_data = data_memory_read_data;
assign rt_address = MEM_rt_address;
assign register_write = MEM_register_write;

2
PipelineProcessor.xpr
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@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="123"/>
<Option Name="WTXSimLaunchSim" Val="140"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>