26 lines
1.1 KiB
Verilog
26 lines
1.1 KiB
Verilog
`timescale 1ns / 1ps
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module InstructionMemory (
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input [31:0] address,
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output reg [31:0] instruction
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);
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always @(*) begin
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case (address[31:2])
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20'd0: instruction <= 32'h3c104000; // lui $s0, 0x4000
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20'd6: instruction <= 32'h2011000a; // addi $s1, $0, 0xa
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20'd11: instruction <= 32'hae110010; // sw $s1, 16($s0)
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20'd16: instruction <= 32'h8e120010; // lw $s2, 16($s0)
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20'd21: instruction <= 32'h2231fffe; // addi $s1, $s1, -2
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20'd26: instruction <= 32'h02329820; // add $s3, $s1, $s2
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20'd31: instruction <= 32'h02529821; // addu $s3, $s2, $s2
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20'd36: instruction <= 32'h02519822; // sub $s3, $s2, $s1
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20'd41: instruction <= 32'h02338823; // subu $s1, $s1, $s3
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20'd46: instruction <= 32'h26310004; // addiu $s1, $s1, 4
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20'd51: instruction <= 32'h02339018; // mul $s2, $s1, $s3
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default: instruction <= 32'h00000000;
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endcase
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end
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endmodule
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