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un-lock-able
2024-07-10 20:36:21 +08:00
parent 6558f7075c
commit 73b0c85399
3 changed files with 14 additions and 11 deletions
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BIN
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
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15
PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
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@@ -7,10 +7,17 @@ module InstructionMemory (
always @(*) begin
case (address[31:2])
20'd0: instruction <= 32'h3c104000; // lui $s0, 0x400
20'd6: instruction <= 32'h2011000a; // addi $s1, $0, 0xa
20'd11: instruction <= 32'hae110010; // sw $s1, 16($s0)
20'd16: instruction <= 32'h8e120010; // lw $s2, 16($s0)
20'd0: instruction <= 32'h3c104000; // lui $s0, 0x4000
20'd6: instruction <= 32'h2011000a; // addi $s1, $0, 0xa
20'd11: instruction <= 32'hae110010; // sw $s1, 16($s0)
20'd16: instruction <= 32'h8e120010; // lw $s2, 16($s0)
20'd21: instruction <= 32'h2231fffe; // addi $s1, $s1, -2
20'd26: instruction <= 32'h02329820; // add $s3, $s1, $s2
20'd31: instruction <= 32'h02529821; // addu $s3, $s2, $s2
20'd36: instruction <= 32'h02519822; // sub $s3, $s2, $s1
20'd41: instruction <= 32'h02338823; // subu $s1, $s1, $s3
20'd46: instruction <= 32'h26310004; // addiu $s1, $s1, 4
20'd51: instruction <= 32'h02339018; // mul $s2, $s1, $s3
default: instruction <= 32'h00000000;
endcase
end

10
PipelineProcessor.xpr
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@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="140"/>
<Option Name="WTXSimLaunchSim" Val="170"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -271,9 +271,7 @@
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
@@ -292,9 +290,7 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>