21 lines
551 B
Verilog
21 lines
551 B
Verilog
`timescale 1ns / 1ps
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module HazardUnit (
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input [1:0] PC_jump,
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input is_loadword,
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input PC_branch,
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output [1:0] IFID_source,
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output IDEX_source,
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output IF_need_stall
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);
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wire is_jump;
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assign is_jump = PC_jump == 2'b01 || PC_jump == 2'b10;
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assign IFID_source = (is_loadword == 1'b1) ? 2'b10 :
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(PC_branch == 1'b1 || is_jump == 1'b1) ? 2'b01 : 2'b00;
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assign IDEX_source = (is_loadword == 1'b1 || PC_branch == 1'b1 || is_jump == 1'b1) ? 1 : 0;
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assign IF_need_stall = (is_loadword == 1'b1) ? 1 : 0;
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endmodule
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