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MipsPipelineProcessor/PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v
2024-07-10 12:06:19 +08:00

12 lines
345 B
Verilog

`timescale 1ns / 1ps
module ImmediateExtender (
input [15:0] immediate,
input [ 1:0] extendop,
output [31:0] extended_immediate
);
assign extended_immediate = (extendop == 2'b00) ? {{16{immediate[15]}}, immediate}:
(extendop == 2'b01) ? {16'h0000, immediate}: {immediate, 16'h0000};
endmodule