40 lines
983 B
Verilog
40 lines
983 B
Verilog
`timescale 1ns / 1ps
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module InstFetch (
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input clk,
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input [31:0] branch_target,
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input [31:0] jump_target,
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input [31:0] jump_register_target,
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input [1:0] PC_jump,
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input PC_branch,
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input need_stall,
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output [31:0] fetched_instruction,
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output [31:0] PC_plus_4
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);
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reg [31:0] PC;
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InstructionMemory instruction_memory (
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.address(PC),
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.instruction(fetched_instruction)
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);
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wire adder_out;
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assign adder_out = PC + 4;
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always @(posedge clk) begin
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if (need_stall) begin
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PC <= PC;
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end else begin
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if (PC_branch) begin
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PC <= branch_target;
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end else begin
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case (PC_jump)
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2'b00: PC <= adder_out;
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2'b01: PC <= jump_target;
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2'b10: PC <= jump_register_target;
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default: PC <= adder_out;
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endcase
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end
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end
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end
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endmodule
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