17 lines
318 B
Verilog
17 lines
318 B
Verilog
`timescale 1ns / 1ps
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module InstructionMemory (
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input [31:0] address,
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output reg [31:0] instruction
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);
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always @(*) begin
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case (address[31:2])
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20'd0: instruction <= 32'h20210001;
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20'd1: instruction <= 32'h08000000;
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default: instruction <= 32'h00000000;
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endcase
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end
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endmodule
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