73 lines
2.4 KiB
Verilog
73 lines
2.4 KiB
Verilog
`timescale 1ns / 1ps
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module MemoryAccess (
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input clk,
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// From prev stage
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input prev_register_write,
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input prev_WB_source,
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input prev_memory_write,
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input [31:0] prev_ALU_result,
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input [31:0] prev_memory_write_data,
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input [4:0] prev_register_write_destination,
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input [4:0] prev_rt_address,
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// From forward unit
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input MEM_write_data_source,
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// From WB
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input [31:0] WB_forwarded_data,
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// To Forward unit
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output [4:0] rt_address,
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// To next stage
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output register_write,
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output WB_source,
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output [31:0] memory_read_data,
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output [31:0] ALU_result,
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output [4:0] register_write_destination,
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// Data memory IO
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output data_memory_write,
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output [31:0] data_memory_address,
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output [31:0] data_memory_write_data,
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input [31:0] data_memory_read_data
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);
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reg MEM_register_write;
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reg MEM_WB_source;
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reg MEM_memory_write;
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reg [31:0] MEM_ALU_result;
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reg [31:0] MEM_memory_write_data;
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reg [4:0] MEM_register_write_destination;
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reg [4:0] MEM_rt_address;
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// wire memory_write_data_include_forward;
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// assign memory_write_data_include_forward = (MEM_write_data_source == 1'b0) ?
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// MEM_memory_write_data : WB_forwarded_data;
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// DataMemory data_memory(
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// .clk(clk),
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// .address(MEM_ALU_result),
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// .write_enable(MEM_memory_write),
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// .write_data(memory_write_data_include_forward),
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// .read_data(memory_read_data)
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// );
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assign data_memory = MEM_memory_write;
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assign data_memory_address = MEM_ALU_result;
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assign data_memory_write_data = (MEM_write_data_source == 1'b0) ?
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MEM_memory_write_data : WB_forwarded_data;
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assign read_data = data_memory_read_data;
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assign rt_address = MEM_rt_address;
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assign register_write = MEM_register_write;
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assign WB_source = MEM_WB_source;
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assign ALU_result = MEM_ALU_result;
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assign register_write_destination = MEM_register_write_destination;
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always @(posedge clk) begin
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MEM_register_write <= prev_register_write;
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MEM_WB_source <= prev_WB_source;
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MEM_memory_write <= prev_memory_write;
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MEM_ALU_result <= prev_ALU_result;
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MEM_memory_write_data <= prev_memory_write_data;
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MEM_register_write_destination <= prev_register_write_destination;
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MEM_rt_address <= prev_rt_address;
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end
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endmodule
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