12 lines
359 B
Verilog
12 lines
359 B
Verilog
`timescale 1ns / 1ps
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module MemoryForward (
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input WB_register_write,
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input [4:0] WB_register_write_address,
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input [4:0] MEM_rt_address,
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output MEM_write_data_source
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);
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assign MEM_write_data_source = (WB_register_write == 1'b1) ?
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((MEM_rt_address != 5'b00000 && WB_register_write_address == MEM_rt_address) ? 1 : 0) : 0;
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endmodule
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