34 lines
1.0 KiB
Verilog
34 lines
1.0 KiB
Verilog
`timescale 1ns / 1ps
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module WriteBack (
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input clk,
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// From prev stage
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input prev_register_write,
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input prev_WB_source,
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input [31:0] prev_memory_read_data,
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input [31:0] prev_ALU_result,
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input [4:0] prev_register_write_destination,
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// To many things, really
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output register_write,
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output [31:0] register_write_data,
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output [4:0] register_write_addr
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);
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reg WB_register_write;
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reg WB_WB_source;
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reg [31:0] WB_memory_read_data;
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reg [31:0] WB_ALU_result;
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reg [4:0] WB_register_write_destination;
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assign register_write = WB_register_write;
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assign register_write_data = (WB_WB_source == 1'b0) ? WB_ALU_result : WB_memory_read_data;
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assign register_write_addr = WB_register_write_destination;
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always @(posedge clk) begin
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WB_register_write <= prev_register_write;
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WB_WB_source <= prev_WB_source;
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WB_memory_read_data <= prev_memory_read_data;
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WB_ALU_result <= prev_ALU_result;
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WB_register_write_destination <= prev_register_write_destination;
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end
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endmodule
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