un-lock-able ee78aabc48 Add ori

2024-07-12 00:02:09 +08:00

PipelineProcessor.cache/ip/2023.2/a/4/a4c5028597ba9ab4

Initial commit

2024-07-10 12:06:19 +08:00

PipelineProcessor.gen/sources_1/ip/phase_locked_loop

Initial commit

2024-07-10 12:06:19 +08:00

PipelineProcessor.ip_user_files

Initial commit

2024-07-10 12:06:19 +08:00

PipelineProcessor.runs/phase_locked_loop_synth_1

Initial commit

2024-07-10 12:06:19 +08:00

PipelineProcessor.sim/sim_1/behav/xsim

Pass hazard test

2024-07-11 11:37:13 +08:00

PipelineProcessor.srcs

Add ori

2024-07-12 00:02:09 +08:00

.gitignore

Initial commit

2024-07-10 12:06:19 +08:00

PipelineProcessor.xpr

Pass hazard test

2024-07-11 11:37:13 +08:00

Description

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322 MiB

Languages

Verilog 39.7%

PureBasic 38.2%

Tcl 11.4%

C 10.7%