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Make compiler happy

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un-lock-able
2024-07-10 13:32:04 +08:00
parent c1e3ac203f
commit 07e6545d2a
19 changed files with 714 additions and 42 deletions
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11
PipelineProcessor.sim/sim_1/behav/xsim/InstFetch.tcl Normal file
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@@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

84
PipelineProcessor.sim/sim_1/behav/xsim/glbl.v Normal file
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@@ -0,0 +1,84 @@
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
parameter GRES_WIDTH = 10000;
parameter GRES_START = 10000;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
wire GRESTORE;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
reg GRESTORE_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
assign (strong1, weak0) GRESTORE = GRESTORE_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
initial begin
GRESTORE_int = 1'b0;
#(GRES_START);
GRESTORE_int = 1'b1;
#(GRES_WIDTH);
GRESTORE_int = 1'b0;
end
endmodule
`endif

11
PipelineProcessor.sim/sim_1/behav/xsim/test_cpu.tcl Normal file
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@@ -0,0 +1,11 @@
set curr_wave [current_wave_config]
if { [string length $curr_wave] == 0 } {
if { [llength [get_objects]] > 0} {
add_wave /
set_property needs_save false [current_wave_config]
} else {
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
}
}
run 1000ns

26
PipelineProcessor.sim/sim_1/behav/xsim/test_cpu_vlog.prj Normal file
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@@ -0,0 +1,26 @@
# compile verilog/system verilog design source files
verilog xil_defaultlib --include "../../../../PipelineProcessor.ip_user_files/ipstatic" \
"../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v" \
"../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/ALU.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/ControlUnit.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/DataMemory.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/Execution.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/ExecutionForward.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/HazardUnit.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/InstDecode.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/InstFetch.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/InstructionMemory.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/MemoryAccess.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/MemoryForward.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/RegisterFile.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/WriteBack.v" \
"../../../../PipelineProcessor.srcs/sources_1/new/CPU.v" \
"../../../../PipelineProcessor.srcs/sim_1/new/test_cpu.v" \
# compile glbl module
verilog xil_defaultlib "glbl.v"
# Do not sort compile order
nosort

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PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb Normal file
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PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/InstFetch_behav/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "InstFetch_behav" "xil_defaultlib.InstFetch" "xil_defaultlib.glbl" -log "elaborate.log"

1
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/InstFetch_behav/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

119
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/InstFetch_behav/obj/xsim_1.c Normal file
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@@ -0,0 +1,119 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/**********************************************************************/
#if defined(_WIN32)
#include "stdio.h"
#define IKI_DLLESPEC __declspec(dllimport)
#else
#define IKI_DLLESPEC
#endif
#include "iki.h"
#include <string.h>
#include <math.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
typedef void (*funcp)(char *, char *);
extern int main(int, char**);
IKI_DLLESPEC extern void execute_4(char*, char *);
IKI_DLLESPEC extern void execute_10(char*, char *);
IKI_DLLESPEC extern void execute_11(char*, char *);
IKI_DLLESPEC extern void execute_12(char*, char *);
IKI_DLLESPEC extern void execute_3(char*, char *);
IKI_DLLESPEC extern void execute_6(char*, char *);
IKI_DLLESPEC extern void execute_7(char*, char *);
IKI_DLLESPEC extern void execute_8(char*, char *);
IKI_DLLESPEC extern void execute_9(char*, char *);
IKI_DLLESPEC extern void execute_13(char*, char *);
IKI_DLLESPEC extern void execute_14(char*, char *);
IKI_DLLESPEC extern void execute_15(char*, char *);
IKI_DLLESPEC extern void execute_16(char*, char *);
IKI_DLLESPEC extern void execute_17(char*, char *);
IKI_DLLESPEC extern void execute_18(char*, char *);
IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
funcp funcTab[16] = {(funcp)execute_4, (funcp)execute_10, (funcp)execute_11, (funcp)execute_12, (funcp)execute_3, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_13, (funcp)execute_14, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)vlog_transfunc_eventcallback};
const int NumRelocateId= 16;
void relocate(char *dp)
{
iki_relocate(dp, "xsim.dir/InstFetch_behav/xsim.reloc", (void **)funcTab, 16);
/*Populate the transaction function pointer field in the whole net structure */
}
void sensitize(char *dp)
{
iki_sensitize(dp, "xsim.dir/InstFetch_behav/xsim.reloc");
}
void simulate(char *dp)
{
iki_schedule_processes_at_time_zero(dp, "xsim.dir/InstFetch_behav/xsim.reloc");
// Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
iki_execute_processes();
// Schedule resolution functions for the multiply driven Verilog nets that have strength
// Schedule transaction functions for the singly driven Verilog nets that have strength
}
#include "iki_bridge.h"
void relocate(char *);
void sensitize(char *);
void simulate(char *);
extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
int main(int argc, char **argv)
{
iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
iki_set_xsimdir_location_if_remapped(argc, argv) ;
iki_set_sv_type_file_path_name("xsim.dir/InstFetch_behav/xsim.svtype");
iki_set_crvs_dump_file_path_name("xsim.dir/InstFetch_behav/xsim.crvsdump");
void* design_handle = iki_create_design("xsim.dir/InstFetch_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
iki_set_rc_trial_count(100);
(void) design_handle;
return iki_simulate_design();
}

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PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/InstFetch_behav/xsim.mem Normal file
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PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/Compile_Options.txt Normal file
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@@ -0,0 +1 @@
--incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "test_cpu_behav" "xil_defaultlib.test_cpu" "xil_defaultlib.glbl" -log "elaborate.log"

1
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/TempBreakPointFile.txt Normal file
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@@ -0,0 +1 @@
Breakpoint File Version 1.0

389
PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/obj/xsim_2.c Normal file
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PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem Normal file
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PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb Normal file
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20
PipelineProcessor.srcs/sim_1/new/test_cpu.v Normal file
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@@ -0,0 +1,20 @@
`timescale 1ns / 1ps
module test_cpu ();
reg sim_clk = 0;
reg reset = 0;
wire [11:0] bcd_control;
wire clk_locked;
initial begin
forever begin
#5 sim_clk <= ~sim_clk;
end
end
CPU cpu(
.hardware_clk(sim_clk),
.reset(reset),
.clock_locked(clk_locked),
.bcd_control(bcd_control)
);
endmodule

38
PipelineProcessor.srcs/sources_1/new/ALU.v
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@@ -4,7 +4,7 @@ module ALU (
input [ 4:0] funct,
input [31:0] in_1,
input [31:0] in_2,
output [31:0] result
output reg [31:0] result
);
wire lt_signed;
@@ -14,24 +14,24 @@ module ALU (
always @(*) begin
case (funct)
5'b00000: result = in_1 & in_2; // 0, and
5'b00001: result = in_1 | in_2; // 1, or
5'b00010: result = in_1 + in_2; // 2, add
5'b00110: result = in_1 - in_2; // 6, sub
5'b00111: result = {31'b0, lt_signed}; // 7, slt signed
5'b01000: result = {31'b0, in_1 < in_2}; // 8, slt unsigned
5'b01100: result = ~(in_1 | in_2); // 12, nor
5'b01101: result = in_1 ^ in_2; // 13, xor
5'b10000: result = in_2 << in_1[4:0]; // 16, sll
5'b10001: result = {31'b0, in_1 == in_2}; // 17, eq
5'b10010: result = {31'b0, ~(in_1 == in_2)}; // 18, neq
5'b10011: result = {31'b0, (in_1[31] == 1'b0 && in_1 != 32'h00000000)}; // 19, gtz
5'b10100: result = {31'b0, in_1[31] == 1'b1}; // 20, ltz
5'b10101: result = {31'b0, (in_1[31] == 1'b1 || in_1 == 32'h00000000)}; // 21, lez
5'b11000: result = {in2 >> in1[4:0]}; // 24, srl
5'b11001: result = {{32{in2[31]}}, in2} >> in1[4:0]; // 25, sra
5'b11010: result = in1 * in2; // 26, mul
default: result = 31'h00000000;
5'b00000: result <= in_1 & in_2; // 0, and
5'b00001: result <= in_1 | in_2; // 1, or
5'b00010: result <= in_1 + in_2; // 2, add
5'b00110: result <= in_1 - in_2; // 6, sub
5'b00111: result <= {31'b0, lt_signed}; // 7, slt signed
5'b01000: result <= {31'b0, in_1 < in_2}; // 8, slt unsigned
5'b01100: result <= ~(in_1 | in_2); // 12, nor
5'b01101: result <= in_1 ^ in_2; // 13, xor
5'b10000: result <= in_2 << in_1[4:0]; // 16, sll
5'b10001: result <= {31'b0, in_1 == in_2}; // 17, eq
5'b10010: result <= {31'b0, ~(in_1 == in_2)}; // 18, neq
5'b10011: result <= {31'b0, (in_1[31] == 1'b0 && in_1 != 32'h00000000)}; // 19, gtz
5'b10100: result <= {31'b0, in_1[31] == 1'b1}; // 20, ltz
5'b10101: result <= {31'b0, (in_1[31] == 1'b1 || in_1 == 32'h00000000)}; // 21, lez
5'b11000: result <= {in_2 >> in_1[4:0]}; // 24, srl
5'b11001: result <= {{32{in_2[31]}}, in_2} >> in_1[4:0]; // 25, sra
5'b11010: result <= in_1 * in_2; // 26, mul
default: result <= 31'h00000000;
endcase
end
endmodule

10
PipelineProcessor.srcs/sources_1/new/CPU.v
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@@ -2,6 +2,7 @@
module CPU (
input hardware_clk,
input reset,
output clock_locked,
output [11:0] bcd_control
);
@@ -9,7 +10,8 @@ module CPU (
wire clk;
phase_locked_loop pll (
.clk_in1 (hardware_clk),
.clk_out1(clk)
.clk_out1(clk),
.locked(clock_locked)
);
// Out of IF
@@ -94,7 +96,7 @@ module CPU (
.PC_branch(EX_PC_branch),
.need_stall(hazard_IF_need_stall),
.fetched_instruction(IF_fetched_instruction),
.PC_plus_4(IF_PC_plus_4),
.PC_plus_4(IF_PC_plus_4)
);
InstDecode instruction_decode (
@@ -195,7 +197,7 @@ module CPU (
.prev_register_write_destination(MEM_register_write_destination),
.register_write(WB_register_write),
.register_write_data(WB_register_write_data),
.register_write_addr(WB_register_write_address),
.register_write_addr(WB_register_write_address)
);
DataMemory data_memory (
@@ -222,7 +224,7 @@ module CPU (
.WB_register_write(WB_register_write),
.WB_register_write_address(WB_register_write_address),
.MEM_rt_address(MEM_rt_address),
.MEM_write_data_source(MEMforward_MEM_write_data_source),
.MEM_write_data_source(MEMforward_MEM_write_data_source)
);
HazardUnit hazard_unit (

16
PipelineProcessor.srcs/sources_1/new/ExecutionForward.v
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@@ -6,32 +6,32 @@ module ExecutionForward (
input [4:0] MEM_register_write_address,
input WB_register_write,
input [4:0] WB_register_write_address,
output [1:0] IDA_source,
output [1:0] IDB_source
output reg [1:0] IDA_source,
output reg [1:0] IDB_source
);
always @(*) begin
if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rs_address &&
EX_rs_address != 5'b00000) begin
IDA_source = 2'b00;
IDA_source <= 2'b00;
end else begin
if (WB_register_write == 1'b1 && WB_register_write_address == EX_rs_address &&
EX_rs_address != 5'b00000) begin
IDA_source = 2'b10;
IDA_source <= 2'b10;
end else begin
IDA_source = 2'b00;
IDA_source <= 2'b00;
end
end
if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rt_address &&
EX_rt_address != 5'b00000) begin
IDB_source = 2'b00;
IDB_source <= 2'b00;
end else begin
if (WB_register_write == 1'b1 && WB_register_write_address == EX_rt_address &&
EX_rt_address != 5'b00000) begin
IDB_source = 2'b10;
IDB_source <= 2'b10;
end else begin
IDB_source = 2'b00;
IDB_source <= 2'b00;
end
end
end

28
PipelineProcessor.xpr
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@@ -60,7 +60,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
<Option Name="WTXSimLaunchSim" Val="0"/>
<Option Name="WTXSimLaunchSim" Val="17"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -209,11 +209,17 @@
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PSRCDIR/sim_1/new/test_cpu.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="InstFetch"/>
<Option Name="TopModule" Val="test_cpu"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
@@ -265,7 +271,9 @@
<Runs Version="1" Minor="21">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
@@ -274,9 +282,7 @@
</Run>
<Run Id="phase_locked_loop_synth_1" Type="Ft3:Synth" SrcSet="phase_locked_loop" Part="xc7a35tfgg484-1" ConstrsSet="phase_locked_loop" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/phase_locked_loop_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/phase_locked_loop_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/phase_locked_loop_synth_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -286,7 +292,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -303,9 +311,7 @@
</Run>
<Run Id="phase_locked_loop_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tfgg484-1" ConstrsSet="phase_locked_loop" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="phase_locked_loop_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/phase_locked_loop_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/phase_locked_loop_impl_1">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>