Test neq

2024-07-10 23:56:40 +08:00
parent acfae7a597
commit aa64c19c8b
3 changed files with 47 additions and 0 deletions
--- a/05test_neq.asm
+++ b/05test_neq.asm
@@ -0,0 +1,35 @@
+    addi    $s1,            $zero,  1
+    nop     
+    nop     
+    nop     
+    nop     
+    bne     $s1,            $s2,    bne_target
+    nop     
+    nop     
+    nop     
+    nop     
+    addi    $s3,            $zero,  1
+    nop     
+    nop     
+    nop     
+    nop     
+
+bne_target:
+    addi    $s2,            $zero,  1
+    nop     
+    nop     
+    nop     
+    nop     
+    bne     $s1,            $s2,    bne_target2
+    nop     
+    nop     
+    nop     
+    nop     
+    addi    $s3,            $zero,  2
+    nop
+    nop
+    nop
+    nop
+
+bne_target2:
+    j       bne_target2
--- a/05test_neq_mars.txt
+++ b/05test_neq_mars.txt
@@ -0,0 +1,7 @@
+20110001
+16320009
+20130001
+20120001
+16320009
+20130002
+0810001e
--- a/create_verilog_from_asm.py
+++ b/create_verilog_from_asm.py
@@ -0,0 +1,5 @@
+file_name = input("File name: ")
+with open(file_name) as fl:
+    file_content = fl.readlines()
+for idx, inst in enumerate(file_content):
+    print("20'd%d: instruction <= 32'h%s;" % (idx, inst.strip()))