Test neq

2024-07-10 23:56:40 +08:00
parent acfae7a597
commit aa64c19c8b
3 changed files with 47 additions and 0 deletions
--- a/create_verilog_from_asm.py
+++ b/create_verilog_from_asm.py
@@ -0,0 +1,5 @@
+file_name = input("File name: ")
+with open(file_name) as fl:
+    file_content = fl.readlines()
+for idx, inst in enumerate(file_content):
+    print("20'd%d: instruction <= 32'h%s;" % (idx, inst.strip()))