unlockable/MipsPipelineProcessor
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initialize data in verilog

Browse Source
This commit is contained in:
un-lock-able
2024-07-13 14:43:17 +08:00
parent 00ba02eb57
commit 43ce61daf9
40 changed files with 3067 additions and 3038 deletions
Download Patch File Download Diff File Expand all files Collapse all files

477
PipelineProcessor.runs/impl_1/CPU.vdi
View File

@@ -3,8 +3,8 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Fri Jul 12 21:05:00 2024
# Process ID: 22952
# Start of session at: Sat Jul 13 14:27:36 2024
# Process ID: 19592
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1
# Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi
@@ -12,14 +12,14 @@
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
#-----------------------------------------------------------
source CPU.tcl -notrace
create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 464.035 ; gain = 185.215
create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 462.727 ; gain = 184.750
Command: link_design -top CPU -part xc7a35tfgg484-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a35tfgg484-1
INFO: [Project 1-454] Reading design checkpoint 'd:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp' for cell 'pll'
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.112 . Memory (MB): peak = 915.762 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 3557 Unisim elements for replacement
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.175 . Memory (MB): peak = 915.922 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 3504 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2023.2
INFO: [Project 1-570] Preparing netlist for logic optimization
@@ -28,18 +28,18 @@ Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/Pipelin
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
INFO: [Timing 38-2] Deriving generated clocks [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
get_clocks: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 1598.367 ; gain = 557.914
get_clocks: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1598.910 ; gain = 559.754
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1598.367 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1598.910 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 1598.367 ; gain = 1120.484
link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 1598.910 ; gain = 1122.715
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
@@ -50,111 +50,112 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.645 . Memory (MB): peak = 1598.367 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1598.910 ; gain = 0.000
Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 16cb45a4f
Ending Cache Timing Information Task | Checksum: 144775da6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.434 . Memory (MB): peak = 1612.133 ; gain = 13.766
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1613.023 ; gain = 14.113
Starting Logic Optimization Task
Phase 1 Initialization
Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 16cb45a4f
Phase 1.1 Core Generation And Design Setup | Checksum: 144775da6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 16cb45a4f
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 144775da6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1980.477 ; gain = 0.000
Phase 1 Initialization | Checksum: 16cb45a4f
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 1 Initialization | Checksum: 144775da6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 2 Timer Update And Timing Data Collection
Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 16cb45a4f
Phase 2.1 Timer Update | Checksum: 144775da6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.355 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.617 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 16cb45a4f
Phase 2.2 Timing Data Collection | Checksum: 144775da6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.379 . Memory (MB): peak = 1980.477 ; gain = 0.000
Phase 2 Timer Update And Timing Data Collection | Checksum: 16cb45a4f
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.640 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 2 Timer Update And Timing Data Collection | Checksum: 144775da6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.380 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.642 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 3 Retarget
INFO: [Opt 31-1566] Pulled 13 inverters resulting in an inversion of 263 pins
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 192618621
Phase 3 Retarget | Checksum: 17395c2ed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.517 . Memory (MB): peak = 1980.477 ; gain = 0.000
Retarget | Checksum: 192618621
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 1 cells
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.901 . Memory (MB): peak = 1972.844 ; gain = 0.000
Retarget | Checksum: 17395c2ed
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 14 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 20b011990
Phase 4 Constant propagation | Checksum: 1c089ccf4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.606 . Memory (MB): peak = 1980.477 ; gain = 0.000
Constant propagation | Checksum: 20b011990
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
Constant propagation | Checksum: 1c089ccf4
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
Phase 5 Sweep
Phase 5 Sweep | Checksum: 1bc044ae4
Phase 5 Sweep | Checksum: 12eb909f8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.749 . Memory (MB): peak = 1980.477 ; gain = 0.000
Sweep | Checksum: 1bc044ae4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
Sweep | Checksum: 12eb909f8
INFO: [Opt 31-389] Phase Sweep created 12 cells and removed 0 cells
Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1bc044ae4
Phase 6 BUFG optimization | Checksum: 12eb909f8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.864 . Memory (MB): peak = 1980.477 ; gain = 0.000
BUFG optimization | Checksum: 1bc044ae4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
BUFG optimization | Checksum: 12eb909f8
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1bc044ae4
Phase 7 Shift Register Optimization | Checksum: 12eb909f8
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.875 . Memory (MB): peak = 1980.477 ; gain = 0.000
Shift Register Optimization | Checksum: 1bc044ae4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
Shift Register Optimization | Checksum: 12eb909f8
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 24e91c234
Phase 8 Post Processing Netlist | Checksum: 17562fe4e
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.902 . Memory (MB): peak = 1980.477 ; gain = 0.000
Post Processing Netlist | Checksum: 24e91c234
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
Post Processing Netlist | Checksum: 17562fe4e
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Phase 9 Finalization
Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 14de2f7bb
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1329e1c39
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 9.2 Verifying Netlist Connectivity
Starting Connectivity Check Task
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1980.477 ; gain = 0.000
Phase 9.2 Verifying Netlist Connectivity | Checksum: 14de2f7bb
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 9.2 Verifying Netlist Connectivity | Checksum: 1329e1c39
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000
Phase 9 Finalization | Checksum: 14de2f7bb
Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 9 Finalization | Checksum: 1329e1c39
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000
Opt_design Change Summary
=========================
@@ -162,7 +163,7 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
-------------------------------------------------------------------------------------------------------------------------
| Retarget | 0 | 1 | 1 |
| Retarget | 0 | 14 | 1 |
| Constant propagation | 0 | 0 | 0 |
| Sweep | 12 | 0 | 0 |
| BUFG optimization | 0 | 0 | 0 |
@@ -171,31 +172,32 @@ Opt_design Change Summary
-------------------------------------------------------------------------------------------------------------------------
Ending Logic Optimization Task | Checksum: 14de2f7bb
Ending Logic Optimization Task | Checksum: 1329e1c39
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.477 ; gain = 0.000
Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1972.844 ; gain = 0.000
Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 14de2f7bb
Ending Power Optimization Task | Checksum: 1329e1c39
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1972.844 ; gain = 0.000
Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 14de2f7bb
Ending Final Cleanup Task | Checksum: 1329e1c39
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.844 ; gain = 0.000
Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1980.477 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 14de2f7bb
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000
Ending Netlist Obfuscation Task | Checksum: 1329e1c39
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1972.844 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1972.844 ; gain = 373.934
INFO: [runtcl-4] Executing : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
Command: report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -203,16 +205,16 @@ INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt.
report_drc completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1980.477 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1980.477 ; gain = 0.000
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.844 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1972.844 ; gain = 0.000
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1980.477 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1980.477 ; gain = 0.000
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 1980.477 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1980.477 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 1980.477 ; gain = 0.000
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1972.844 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.844 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1972.844 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1972.844 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_opt.dcp' has been generated.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -232,59 +234,59 @@ Starting Placer Task
Phase 1 Placer Initialization
Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1980.477 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11b2d87cf
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9a573811
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.009 . Memory (MB): peak = 1980.477 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1972.844 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: e3d58ae7
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 161645cda
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1980.477 ; gain = 0.000
Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1db20e775
Phase 1.3 Build Placer Netlist Model | Checksum: 254135206
Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1db20e775
Phase 1.4 Constrain Clocks/Macros | Checksum: 254135206
Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2032.707 ; gain = 52.230
Phase 1 Placer Initialization | Checksum: 1db20e775
Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 1 Placer Initialization | Checksum: 254135206
Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 2 Global Placement
Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 156b1aef4
Phase 2.1 Floorplanning | Checksum: 21edfd7da
Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1d86be86e
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 187f6e72f
Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1d86be86e
Phase 2.3 Post-Processing in Floorplanning | Checksum: 187f6e72f
Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 2.4 Global Placement Core
Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 1400d07dd
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 2bcb2d97a
Time (s): cpu = 00:00:03 ; elapsed = 00:00:10 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 78 LUT instances to create LUTNM shape
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 61 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 37 nets or LUTs. Breaked 0 LUT, combined 37 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-1138] End 1 Pass. Optimized 29 nets or LUTs. Breaked 0 LUT, combined 29 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
@@ -295,7 +297,7 @@ INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was
INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2032.707 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2040.230 ; gain = 0.000
Summary of Physical Synthesis Optimizations
============================================
@@ -304,7 +306,7 @@ Summary of Physical Synthesis Optimizations
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
| LUT Combining | 0 | 37 | 37 | 0 | 1 | 00:00:00 |
| LUT Combining | 0 | 29 | 29 | 0 | 1 | 00:00:00 |
| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
@@ -313,59 +315,59 @@ Summary of Physical Synthesis Optimizations
| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
| Total | 0 | 37 | 37 | 0 | 4 | 00:00:00 |
| Total | 0 | 29 | 29 | 0 | 4 | 00:00:00 |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1f5974df5
Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1cd490dfe
Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 2032.707 ; gain = 52.230
Phase 2.4 Global Placement Core | Checksum: 15c812e1b
Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 2.4 Global Placement Core | Checksum: 2593ef06b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.707 ; gain = 52.230
Phase 2 Global Placement | Checksum: 15c812e1b
Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 2 Global Placement | Checksum: 2593ef06b
Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 3 Detail Placement
Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1da65e99f
Phase 3.1 Commit Multi Column Macros | Checksum: 24c2e5196
Time (s): cpu = 00:00:04 ; elapsed = 00:00:13 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1d55c087b
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b29cdebe
Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1214d70ca
Phase 3.3 Area Swap Optimization | Checksum: 1fd1f47c3
Time (s): cpu = 00:00:05 ; elapsed = 00:00:14 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 174ca9207
Phase 3.4 Pipeline Register Optimization | Checksum: 1bbf6b047
Time (s): cpu = 00:00:05 ; elapsed = 00:00:14 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1eb9f62f7
Phase 3.5 Small Shape Detail Placement | Checksum: 1f0217d20
Time (s): cpu = 00:00:06 ; elapsed = 00:00:28 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:09 ; elapsed = 00:00:26 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1badb8766
Phase 3.6 Re-assign LUT pins | Checksum: 149d47d39
Time (s): cpu = 00:00:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 1ad982255
Phase 3.7 Pipeline Register Optimization | Checksum: 14f4d2963
Time (s): cpu = 00:00:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2032.707 ; gain = 52.230
Phase 3 Detail Placement | Checksum: 1ad982255
Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 3 Detail Placement | Checksum: 14f4d2963
Time (s): cpu = 00:00:06 ; elapsed = 00:00:29 . Memory (MB): peak = 2032.707 ; gain = 52.230
Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387
Phase 4 Post Placement Optimization and Clean-Up
@@ -373,7 +375,7 @@ Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 25abda1d4
Post Placement Optimization Initialization | Checksum: 1b9a7b723
Phase 4.1.1.1 BUFG Insertion
@@ -381,34 +383,34 @@ Starting Physical Synthesis Task
Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=1.540 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 1a16c95e6
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.040 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 19276cbb6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.702 . Memory (MB): peak = 2079.688 ; gain = 10.484
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.744 . Memory (MB): peak = 2088.574 ; gain = 13.941
INFO: [Place 46-33] Processed net data_memory/reset, BUFG insertion was skipped due to placement/routing conflicts.
INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 1a16c95e6
Ending Physical Synthesis Task | Checksum: 19276cbb6
Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2081.648 ; gain = 12.445
Phase 4.1.1.1 BUFG Insertion | Checksum: 25abda1d4
Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2090.840 ; gain = 16.207
Phase 4.1.1.1 BUFG Insertion | Checksum: 1b9a7b723
Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996
Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=1.540. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 189e73d35
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.040. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1b853f6e8
Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996
Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
Phase 4.1 Post Commit Optimization | Checksum: 189e73d35
Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996
Phase 4.1 Post Commit Optimization | Checksum: 1b853f6e8
Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996
Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 189e73d35
Phase 4.2 Post Placement Cleanup | Checksum: 1b853f6e8
Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
Phase 4.3 Placer Reporting
@@ -418,7 +420,7 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
| | Global Congestion | Short Congestion |
| Direction | Region Size | Region Size |
|___________|___________________|___________________|
| North| 2x2| 2x2|
| North| 4x4| 2x2|
|___________|___________________|___________________|
| South| 1x1| 1x1|
|___________|___________________|___________________|
@@ -427,42 +429,42 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
| West| 1x1| 1x1|
|___________|___________________|___________________|
Phase 4.3.1 Print Estimated Congestion | Checksum: 189e73d35
Phase 4.3.1 Print Estimated Congestion | Checksum: 1b853f6e8
Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
Phase 4.3 Placer Reporting | Checksum: 189e73d35
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
Phase 4.3 Placer Reporting | Checksum: 1b853f6e8
Time (s): cpu = 00:00:07 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2081.648 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2091.523 ; gain = 0.000
Time (s): cpu = 00:00:08 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
Phase 4 Post Placement Optimization and Clean-Up | Checksum: d7614f21
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 10fcc6d31
Time (s): cpu = 00:00:08 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
Ending Placer Task | Checksum: bc3137e6
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
Ending Placer Task | Checksum: 51a85dd7
Time (s): cpu = 00:00:08 ; elapsed = 00:00:34 . Memory (MB): peak = 2081.648 ; gain = 101.172
65 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:35 . Memory (MB): peak = 2081.648 ; gain = 101.172
place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.523 ; gain = 118.680
INFO: [runtcl-4] Executing : report_io -file CPU_io_placed.rpt
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 2081.648 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 2091.523 ; gain = 0.000
INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.050 . Memory (MB): peak = 2081.648 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 2091.523 ; gain = 0.000
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 2096.543 ; gain = 1.004
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.543 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2096.543 ; gain = 0.000
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 2106.918 ; gain = 1.973
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2106.918 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.918 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2096.543 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.027 . Memory (MB): peak = 2096.543 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2096.543 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2096.543 ; gain = 1.004
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2106.918 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2106.918 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2106.918 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2106.918 ; gain = 1.973
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_placed.dcp' has been generated.
Command: phys_opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -470,23 +472,23 @@ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc
Starting Initial Update Timing Task
Time (s): cpu = 00:00:01 ; elapsed = 00:00:03 . Memory (MB): peak = 2143.457 ; gain = 46.914
Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2153.953 ; gain = 47.035
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2168.809 ; gain = 7.066
Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2169.680 ; gain = 0.871
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2169.680 ; gain = 0.000
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2179.293 ; gain = 7.062
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2179.293 ; gain = 7.062
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2179.293 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 2169.680 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2169.680 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2169.680 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2169.680 ; gain = 7.938
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2179.293 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2179.293 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2179.293 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2179.293 ; gain = 7.062
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_physopt.dcp' has been generated.
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -501,30 +503,30 @@ Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
Phase 1 Build RT Design
Checksum: PlaceDB: 835e865f ConstDB: 0 ShapeSum: 38d2b187 RouteDB: 0
Post Restoration Checksum: NetGraph: 3533f183 | NumContArr: bffdc8ea | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 27a83afa7
Checksum: PlaceDB: 4fa4d64c ConstDB: 0 ShapeSum: 203878b RouteDB: 0
Post Restoration Checksum: NetGraph: c8a283dc | NumContArr: aad6ec74 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 2f8cb658a
Time (s): cpu = 00:00:06 ; elapsed = 00:00:13 . Memory (MB): peak = 2287.406 ; gain = 85.613
Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008
Phase 2 Router Initialization
Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 27a83afa7
Phase 2.1 Fix Topology Constraints | Checksum: 2f8cb658a
Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2287.414 ; gain = 85.621
Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008
Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 27a83afa7
Phase 2.2 Pre Route Cleanup | Checksum: 2f8cb658a
Time (s): cpu = 00:00:06 ; elapsed = 00:00:14 . Memory (MB): peak = 2287.414 ; gain = 85.621
Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008
Number of Nodes with overlaps = 0
Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 17a8d6394
Phase 2.3 Update Timing | Checksum: 201a59748
Time (s): cpu = 00:00:08 ; elapsed = 00:00:18 . Memory (MB): peak = 2305.191 ; gain = 103.398
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.776 | TNS=0.000 | WHS=-0.119 | THS=-29.698|
Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 2307.527 ; gain = 96.730
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.230 | TNS=0.000 | WHS=-0.144 | THS=-28.052|
Router Utilization Summary
@@ -533,86 +535,93 @@ Router Utilization Summary
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
Number of Failed Nets = 21867
Number of Failed Nets = 21997
(Failed Nets is the sum of unrouted and partially routed nets)
Number of Unrouted Nets = 21867
Number of Unrouted Nets = 21997
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 2 Router Initialization | Checksum: 17e574e9c
Phase 2 Router Initialization | Checksum: 276df3972
Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.195 ; gain = 145.402
Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2345.027 ; gain = 134.230
Phase 3 Initial Routing
Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 17e574e9c
Phase 3.1 Global Routing | Checksum: 276df3972
Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.195 ; gain = 145.402
Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2345.027 ; gain = 134.230
Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 272722ad6
Phase 3.2 Initial Net Routing | Checksum: 1646cdf4d
Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 2350.590 ; gain = 148.797
Phase 3 Initial Routing | Checksum: 272722ad6
Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 2349.422 ; gain = 138.625
Phase 3 Initial Routing | Checksum: 1646cdf4d
Time (s): cpu = 00:00:10 ; elapsed = 00:00:21 . Memory (MB): peak = 2350.590 ; gain = 148.797
Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 2349.422 ; gain = 138.625
Phase 4 Rip-up And Reroute
Phase 4.1 Global Iteration 0
Number of Nodes with overlaps = 2990
Number of Nodes with overlaps = 252
Number of Nodes with overlaps = 65
Number of Nodes with overlaps = 17
Number of Nodes with overlaps = 6
Number of Nodes with overlaps = 3178
Number of Nodes with overlaps = 255
Number of Nodes with overlaps = 41
Number of Nodes with overlaps = 12
Number of Nodes with overlaps = 2
Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.677 | TNS=0.000 | WHS=N/A | THS=N/A |
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 4.1 Global Iteration 0 | Checksum: 288010d2c
Phase 4.1 Global Iteration 0 | Checksum: 3741328e8
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949
Phase 4 Rip-up And Reroute | Checksum: 288010d2c
Time (s): cpu = 00:00:19 ; elapsed = 00:00:31 . Memory (MB): peak = 2352.559 ; gain = 141.762
Phase 4 Rip-up And Reroute | Checksum: 3741328e8
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949
Time (s): cpu = 00:00:19 ; elapsed = 00:00:31 . Memory (MB): peak = 2352.559 ; gain = 141.762
Phase 5 Delay and Skew Optimization
Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 288010d2c
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949
Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 2b9958991
Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679 | TNS=0.000 | WHS=N/A | THS=N/A |
Phase 5.1 Delay CleanUp | Checksum: 2b9958991
Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762
Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 288010d2c
Phase 5.2 Clock Skew Optimization | Checksum: 2b9958991
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949
Phase 5 Delay and Skew Optimization | Checksum: 288010d2c
Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762
Phase 5 Delay and Skew Optimization | Checksum: 2b9958991
Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2358.742 ; gain = 156.949
Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762
Phase 6 Post Hold Fix
Phase 6.1 Hold Fix Iter
Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 271761283
Phase 6.1.1 Update Timing | Checksum: 2903d569b
Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.677 | TNS=0.000 | WHS=0.055 | THS=0.000 |
Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679 | TNS=0.000 | WHS=0.070 | THS=0.000 |
Phase 6.1 Hold Fix Iter | Checksum: 271761283
Phase 6.1 Hold Fix Iter | Checksum: 2ecebe266
Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949
Phase 6 Post Hold Fix | Checksum: 271761283
Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762
Phase 6 Post Hold Fix | Checksum: 2ecebe266
Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949
Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762
Phase 7 Route finalize
Router Utilization Summary
Global Vertical Routing Utilization = 13.8992 %
Global Horizontal Routing Utilization = 14.3475 %
Global Vertical Routing Utilization = 16.0809 %
Global Horizontal Routing Utilization = 14.8794 %
Routable Net Status*
*Does not include unroutable nets such as driverless and loadless.
Run report_route_status for detailed report.
@@ -622,44 +631,44 @@ Router Utilization Summary
Number of Partially Routed Nets = 0
Number of Node Overlaps = 0
Phase 7 Route finalize | Checksum: 271761283
Phase 7 Route finalize | Checksum: 2ecebe266
Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2358.742 ; gain = 156.949
Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762
Phase 8 Verifying routed nets
Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 271761283
Phase 8 Verifying routed nets | Checksum: 2ecebe266
Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2360.758 ; gain = 158.965
Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2354.578 ; gain = 143.781
Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 20252a6c4
Phase 9 Depositing Routes | Checksum: 2aa639e35
Time (s): cpu = 00:00:13 ; elapsed = 00:00:33 . Memory (MB): peak = 2361.215 ; gain = 159.422
Time (s): cpu = 00:00:20 ; elapsed = 00:00:34 . Memory (MB): peak = 2354.578 ; gain = 143.781
Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=2.677 | TNS=0.000 | WHS=0.055 | THS=0.000 |
INFO: [Route 35-57] Estimated Timing Summary | WNS=2.679 | TNS=0.000 | WHS=0.070 | THS=0.000 |
INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 20252a6c4
Phase 10 Post Router Timing | Checksum: 2aa639e35
Time (s): cpu = 00:00:13 ; elapsed = 00:00:34 . Memory (MB): peak = 2361.215 ; gain = 159.422
Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781
INFO: [Route 35-16] Router Completed Successfully
Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: d1fb966c
Phase 11 Post-Route Event Processing | Checksum: 6f450aed
Time (s): cpu = 00:00:13 ; elapsed = 00:00:35 . Memory (MB): peak = 2361.215 ; gain = 159.422
Ending Routing Task | Checksum: d1fb966c
Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781
Ending Routing Task | Checksum: 6f450aed
Time (s): cpu = 00:00:14 ; elapsed = 00:00:35 . Memory (MB): peak = 2361.215 ; gain = 159.422
Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781
Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
88 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
90 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:36 . Memory (MB): peak = 2361.215 ; gain = 191.535
route_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:36 . Memory (MB): peak = 2354.578 ; gain = 175.285
INFO: [runtcl-4] Executing : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
Command: report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -672,14 +681,14 @@ INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2429.797 ; gain = 68.582
report_methodology: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2435.902 ; gain = 81.324
INFO: [runtcl-4] Executing : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
Command: report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
Finished Running Vector-less Activity Propagation
98 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
100 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file CPU_route_status.rpt -pb CPU_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file CPU_timing_summary_routed.rpt -pb CPU_timing_summary_routed.pb -rpx CPU_timing_summary_routed.rpx -warn_on_violation
@@ -692,16 +701,16 @@ INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU_bus_sk
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-480] Writing timing data to binary archive.
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.038 . Memory (MB): peak = 2488.125 ; gain = 4.934
Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2488.125 ; gain = 0.000
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2488.125 ; gain = 0.000
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 2496.238 ; gain = 3.922
Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2497.543 ; gain = 1.305
Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2497.543 ; gain = 0.000
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.215 . Memory (MB): peak = 2488.125 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2488.125 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2488.125 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2488.125 ; gain = 4.934
Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.221 . Memory (MB): peak = 2497.543 ; gain = 0.000
Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2497.543 ; gain = 0.000
Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2497.543 ; gain = 0.000
Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2497.543 ; gain = 5.227
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_routed.dcp' has been generated.
Command: write_bitstream -force CPU.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -745,5 +754,5 @@ INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT dev
INFO: [Common 17-83] Releasing license: Implementation
14 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2951.012 ; gain = 462.887
INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 21:07:14 2024...
write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2966.875 ; gain = 469.332
INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 14:30:07 2024...

2
PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Fri Jul 12 21:06:59 2024
| Date : Sat Jul 13 14:29:52 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx
| Design : CPU

36
PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Fri Jul 12 21:06:59 2024
| Date : Sat Jul 13 14:29:52 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_clock_utilization -file CPU_clock_utilization_routed.rpt
| Design : CPU
@@ -50,7 +50,7 @@ Table of Contents
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+
| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 6 | 18130 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/clkout1_buf/O | pll/inst/clk_out1 |
| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 6 | 18132 | 0 | 20.000 | clk_out1_phase_locked_loop | pll/inst/clkout1_buf/O | pll/inst/clk_out1 |
| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y1 | n/a | 1 | 1 | 0 | 20.000 | clkfbout_phase_locked_loop | pll/inst/clkf_buf/O | pll/inst/clkfbout_buf_phase_locked_loop |
+-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+----------------------------+------------------------+-----------------------------------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
@@ -78,12 +78,12 @@ Table of Contents
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1534 | 1200 | 474 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3394 | 1500 | 972 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2590 | 1200 | 888 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4413 | 1500 | 1301 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4412 | 1800 | 855 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 1787 | 950 | 508 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
| X0Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 1517 | 1200 | 460 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y0 | 2 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3911 | 1500 | 1072 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2799 | 1200 | 937 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 3610 | 1500 | 1055 | 450 | 0 | 40 | 0 | 20 | 0 | 20 |
| X0Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 4277 | 1800 | 774 | 400 | 0 | 20 | 0 | 10 | 0 | 20 |
| X1Y2 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 2018 | 950 | 601 | 300 | 0 | 10 | 0 | 5 | 0 | 20 |
+-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
* Global Clock column represents track count; while other columns represents cell counts
@@ -107,7 +107,7 @@ All Modules
+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
| g0 | BUFG/O | n/a | clk_out1_phase_locked_loop | 20.000 | {0.000 10.000} | 18130 | 0 | 0 | 0 | pll/inst/clk_out1 |
| g0 | BUFG/O | n/a | clk_out1_phase_locked_loop | 20.000 | {0.000 10.000} | 18132 | 0 | 0 | 0 | pll/inst/clk_out1 |
+-----------+-----------------+-------------------+----------------------------+-------------+----------------+-------------+----------+----------------+----------+-------------------+
* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
** IO Loads column represents load cell count of IO types
@@ -118,9 +118,9 @@ All Modules
+----+-------+-------+-----------------------+
| | X0 | X1 | HORIZONTAL PROG DELAY |
+----+-------+-------+-----------------------+
| Y2 | 4412 | 1787 | 0 |
| Y1 | 2590 | 4413 | 0 |
| Y0 | 1534 | 3394 | 0 |
| Y2 | 4277 | 2018 | 0 |
| Y1 | 2799 | 3610 | 0 |
| Y0 | 1517 | 3911 | 0 |
+----+-------+-------+-----------------------+
@@ -153,7 +153,7 @@ All Modules
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| g0 | n/a | BUFG/O | None | 1534 | 0 | 1534 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
| g0 | n/a | BUFG/O | None | 1517 | 0 | 1517 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
** Non-Clock Loads column represents cell count of non-clock pin loads
@@ -166,7 +166,7 @@ All Modules
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
| g0 | n/a | BUFG/O | None | 3394 | 0 | 3394 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
| g0 | n/a | BUFG/O | None | 3911 | 0 | 3911 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | pll/inst/clkfbout_buf_phase_locked_loop |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
@@ -180,7 +180,7 @@ All Modules
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| g0 | n/a | BUFG/O | None | 2590 | 0 | 2590 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
| g0 | n/a | BUFG/O | None | 2799 | 0 | 2799 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
** Non-Clock Loads column represents cell count of non-clock pin loads
@@ -193,7 +193,7 @@ All Modules
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| g0 | n/a | BUFG/O | None | 4413 | 0 | 4413 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
| g0 | n/a | BUFG/O | None | 3610 | 0 | 3610 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
** Non-Clock Loads column represents cell count of non-clock pin loads
@@ -206,7 +206,7 @@ All Modules
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| g0 | n/a | BUFG/O | None | 4412 | 0 | 4412 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
| g0 | n/a | BUFG/O | None | 4277 | 0 | 4277 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
** Non-Clock Loads column represents cell count of non-clock pin loads
@@ -219,7 +219,7 @@ All Modules
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
| g0 | n/a | BUFG/O | None | 1787 | 0 | 1787 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
| g0 | n/a | BUFG/O | None | 2018 | 0 | 2018 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pll/inst/clk_out1 |
+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
** Non-Clock Loads column represents cell count of non-clock pin loads

1110
PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt
View File

File diff suppressed because it is too large Load Diff

2
PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Fri Jul 12 21:05:24 2024
| Date : Sat Jul 13 14:28:18 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
| Design : CPU

2
PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Fri Jul 12 21:06:47 2024
| Date : Sat Jul 13 14:29:40 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
| Design : CPU

2
PipelineProcessor.runs/impl_1/CPU_io_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Fri Jul 12 21:06:00 2024
| Date : Sat Jul 13 14:28:53 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_io -file CPU_io_placed.rpt
| Design : CPU

2
PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Fri Jul 12 21:06:53 2024
| Date : Sat Jul 13 14:29:46 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
| Design : CPU

BIN
PipelineProcessor.runs/impl_1/CPU_opt.dcp
View File

Binary file not shown.

BIN
PipelineProcessor.runs/impl_1/CPU_physopt.dcp
View File

Binary file not shown.

BIN
PipelineProcessor.runs/impl_1/CPU_placed.dcp
View File

Binary file not shown.

29
PipelineProcessor.runs/impl_1/CPU_power_routed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Fri Jul 12 21:06:57 2024
| Date : Sat Jul 13 14:29:51 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
| Design : CPU
@@ -30,10 +30,10 @@ Table of Contents
----------
+--------------------------+--------------+
| Total On-Chip Power (W) | 0.187 |
| Total On-Chip Power (W) | 0.189 |
| Design Power Budget (W) | Unspecified* |
| Power Budget Margin (W) | NA |
| Dynamic (W) | 0.119 |
| Dynamic (W) | 0.120 |
| Device Static (W) | 0.069 |
| Effective TJA (C/W) | 2.8 |
| Max Ambient (C) | 84.5 |
@@ -52,19 +52,19 @@ Table of Contents
+----------------+-----------+----------+-----------+-----------------+
| On-Chip | Power (W) | Used | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Clocks | 0.015 | 5 | --- | --- |
| Slice Logic | 0.002 | 30077 | --- | --- |
| LUT as Logic | 0.002 | 8003 | 20800 | 38.48 |
| Clocks | 0.016 | 5 | --- | --- |
| Slice Logic | 0.003 | 30286 | --- | --- |
| LUT as Logic | 0.003 | 8337 | 20800 | 40.08 |
| CARRY4 | <0.001 | 39 | 8150 | 0.48 |
| Register | <0.001 | 18130 | 41600 | 43.58 |
| F7/F8 Muxes | <0.001 | 3514 | 32600 | 10.78 |
| Register | <0.001 | 18132 | 41600 | 43.59 |
| F7/F8 Muxes | <0.001 | 3461 | 32600 | 10.62 |
| Others | 0.000 | 12 | --- | --- |
| Signals | 0.002 | 21867 | --- | --- |
| Signals | 0.002 | 21997 | --- | --- |
| PLL | 0.099 | 1 | 5 | 20.00 |
| DSPs | <0.001 | 3 | 90 | 3.33 |
| I/O | <0.001 | 15 | 250 | 6.00 |
| Static Power | 0.069 | | | |
| Total | 0.187 | | | |
| Total | 0.189 | | | |
+----------------+-----------+----------+-----------+-----------------+
@@ -74,7 +74,7 @@ Table of Contents
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint | 1.000 | 0.038 | 0.029 | 0.010 | NA | Unspecified | NA |
| Vccint | 1.000 | 0.040 | 0.030 | 0.010 | NA | Unspecified | NA |
| Vccaux | 1.800 | 0.063 | 0.050 | 0.013 | NA | Unspecified | NA |
| Vcco33 | 3.300 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
@@ -145,13 +145,14 @@ Table of Contents
+----------------------+-----------+
| Name | Power (W) |
+----------------------+-----------+
| CPU | 0.119 |
| CPU | 0.120 |
| data_memory | 0.014 |
| instruction_decode | 0.002 |
| instruction_fetch | 0.002 |
| register_file | 0.001 |
| instruction_fetch | 0.001 |
| pll | 0.100 |
| inst | 0.100 |
| write_back | 0.001 |
| write_back | 0.002 |
+----------------------+-----------+

BIN
PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb
View File

Binary file not shown.

BIN
PipelineProcessor.runs/impl_1/CPU_route_status.pb
View File

Binary file not shown.

10
PipelineProcessor.runs/impl_1/CPU_route_status.rpt
View File

@@ -1,11 +1,11 @@
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 30302 :
# of nets not needing routing.......... : 8428 :
# of internally routed nets........ : 8428 :
# of routable nets..................... : 21874 :
# of fully routed nets............. : 21874 :
# of logical nets.......................... : 30511 :
# of nets not needing routing.......... : 8507 :
# of internally routed nets........ : 8507 :
# of routable nets..................... : 22004 :
# of fully routed nets............. : 22004 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :

BIN
PipelineProcessor.runs/impl_1/CPU_routed.dcp
View File

Binary file not shown.

BIN
PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb
View File

Binary file not shown.

3739
PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt
View File

File diff suppressed because it is too large Load Diff

BIN
PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb
View File

Binary file not shown.

53
PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Fri Jul 12 21:06:00 2024
| Date : Sat Jul 13 14:28:53 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
| Design : CPU
@@ -32,13 +32,13 @@ Table of Contents
+-------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs | 8003 | 0 | 0 | 20800 | 38.48 |
| LUT as Logic | 8003 | 0 | 0 | 20800 | 38.48 |
| Slice LUTs | 8337 | 0 | 0 | 20800 | 40.08 |
| LUT as Logic | 8337 | 0 | 0 | 20800 | 40.08 |
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 18130 | 0 | 0 | 41600 | 43.58 |
| Register as Flip Flop | 18130 | 0 | 0 | 41600 | 43.58 |
| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 |
| Register as Flip Flop | 18132 | 0 | 0 | 41600 | 43.59 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 2426 | 0 | 0 | 16300 | 14.88 |
| F7 Muxes | 2373 | 0 | 0 | 16300 | 14.56 |
| F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 |
+-------------------------+-------+-------+------------+-----------+-------+
* Warning! LUT value is adjusted to account for LUT combining.
@@ -58,8 +58,8 @@ Table of Contents
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 18130 | Yes | Reset | - |
| 368 | Yes | Set | - |
| 17764 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -69,21 +69,21 @@ Table of Contents
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+--------------------------------------------+-------+-------+------------+-----------+-------+
| Slice | 7420 | 0 | 0 | 8150 | 91.04 |
| SLICEL | 5250 | 0 | | | |
| SLICEM | 2170 | 0 | | | |
| LUT as Logic | 8003 | 0 | 0 | 20800 | 38.48 |
| Slice | 7477 | 0 | 0 | 8150 | 91.74 |
| SLICEL | 5277 | 0 | | | |
| SLICEM | 2200 | 0 | | | |
| LUT as Logic | 8337 | 0 | 0 | 20800 | 40.08 |
| using O5 output only | 0 | | | | |
| using O6 output only | 7624 | | | | |
| using O5 and O6 | 379 | | | | |
| using O6 output only | 8032 | | | | |
| using O5 and O6 | 305 | | | | |
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
| LUT as Distributed RAM | 0 | 0 | | | |
| LUT as Shift Register | 0 | 0 | | | |
| Slice Registers | 18130 | 0 | 0 | 41600 | 43.58 |
| Register driven from within the Slice | 1232 | | | | |
| Register driven from outside the Slice | 16898 | | | | |
| LUT in front of the register is unused | 14968 | | | | |
| LUT in front of the register is used | 1930 | | | | |
| Slice Registers | 18132 | 0 | 0 | 41600 | 43.59 |
| Register driven from within the Slice | 1478 | | | | |
| Register driven from outside the Slice | 16654 | | | | |
| LUT in front of the register is unused | 14681 | | | | |
| LUT in front of the register is used | 1973 | | | | |
| Unique Control Sets | 547 | | 0 | 8150 | 6.71 |
+--------------------------------------------+-------+-------+------------+-----------+-------+
* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -180,14 +180,15 @@ Table of Contents
+-----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+-----------+-------+---------------------+
| FDRE | 18130 | Flop & Latch |
| LUT6 | 6947 | LUT |
| MUXF7 | 2426 | MuxFx |
| FDRE | 17764 | Flop & Latch |
| LUT6 | 7147 | LUT |
| MUXF7 | 2373 | MuxFx |
| MUXF8 | 1088 | MuxFx |
| LUT5 | 720 | LUT |
| LUT4 | 300 | LUT |
| LUT3 | 231 | LUT |
| LUT2 | 183 | LUT |
| LUT5 | 831 | LUT |
| FDSE | 368 | Flop & Latch |
| LUT4 | 279 | LUT |
| LUT3 | 229 | LUT |
| LUT2 | 155 | LUT |
| CARRY4 | 39 | CarryLogic |
| OBUF | 13 | IO |
| DSP48E1 | 3 | Block Arithmetic |

2
PipelineProcessor.runs/impl_1/clockInfo.txt
View File

@@ -1,6 +1,6 @@
-------------------------------------
| Tool Version : Vivado v.2023.2
| Date : Fri Jul 12 21:05:29 2024
| Date : Sat Jul 13 14:28:25 2024
| Host : Viviana
| Design : design_1
| Device : xc7a35t-fgg484-1--

BIN
PipelineProcessor.runs/impl_1/init_design.pb
View File

Binary file not shown.

BIN
PipelineProcessor.runs/impl_1/opt_design.pb
View File

Binary file not shown.

BIN
PipelineProcessor.runs/impl_1/phys_opt_design.pb
View File

Binary file not shown.

BIN
PipelineProcessor.runs/impl_1/place_design.pb
View File

Binary file not shown.

BIN
PipelineProcessor.runs/impl_1/route_design.pb
View File

Binary file not shown.

4
PipelineProcessor.runs/impl_1/vivado.jou
View File

@@ -3,8 +3,8 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Fri Jul 12 21:05:00 2024
# Process ID: 22952
# Start of session at: Sat Jul 13 14:27:36 2024
# Process ID: 19592
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1
# Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi

BIN
PipelineProcessor.runs/impl_1/vivado.pb
View File

Binary file not shown.

BIN
PipelineProcessor.runs/impl_1/write_bitstream.pb
View File

Binary file not shown.

BIN
PipelineProcessor.runs/synth_1/CPU.dcp
View File

Binary file not shown.

103
PipelineProcessor.runs/synth_1/CPU.vds
View File

@@ -3,8 +3,8 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Fri Jul 12 21:03:30 2024
# Process ID: 19744
# Start of session at: Sat Jul 13 14:22:20 2024
# Process ID: 3472
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1
# Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds
@@ -12,7 +12,7 @@
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
#-----------------------------------------------------------
source CPU.tcl -notrace
create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 462.926 ; gain = 182.984
create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:22 . Memory (MB): peak = 463.508 ; gain = 184.387
Command: read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
INFO: [Vivado 12-5825] Read reference checkpoint from D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp for incremental synthesis
INFO: [Vivado 12-7989] Please ensure there are no constraint changes
@@ -25,13 +25,13 @@ INFO: [Designutils 20-5440] No compile time benefit to using incremental synthes
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 23648
INFO: [Synth 8-7075] Helper process launched with PID 30200
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1306.855 ; gain = 438.977
Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:18 . Memory (MB): peak = 1308.621 ; gain = 440.629
---------------------------------------------------------------------------------
INFO: [Synth 8-6157] synthesizing module 'CPU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2]
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-19744-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-19744-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-3472-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-3472-Viviana/realtime/phase_locked_loop_stub.v:6]
INFO: [Synth 8-6157] synthesizing module 'InstFetch' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2]
INFO: [Synth 8-6157] synthesizing module 'InstructionMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
INFO: [Synth 8-6155] done synthesizing module 'InstructionMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
@@ -66,18 +66,18 @@ WARNING: [Synth 8-7129] Port address[0] in module DataMemory is either unconnect
WARNING: [Synth 8-7129] Port address[1] in module InstructionMemory is either unconnected or has no load
WARNING: [Synth 8-7129] Port address[0] in module InstructionMemory is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1476.648 ; gain = 608.770
Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1476.648 ; gain = 608.770
Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1476.648 ; gain = 608.770
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.173 . Memory (MB): peak = 1476.648 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.793 . Memory (MB): peak = 1478.609 ; gain = 0.000
INFO: [Project 1-570] Preparing netlist for logic optimization
Processing XDC Constraints
@@ -90,22 +90,22 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi
Resolution: To avoid this warning, move constraints listed in [.Xil/CPU_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1584.652 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1578.020 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.063 . Memory (MB): peak = 1584.652 ; gain = 0.000
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.243 . Memory (MB): peak = 1578.020 ; gain = 0.000
INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.652 ; gain = 716.773
Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tfgg484-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.652 ; gain = 716.773
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
@@ -114,10 +114,10 @@ Applied set_property IO_BUFFER_TYPE = NONE for hardware_clk. (constraint file d
Applied set_property CLOCK_BUFFER_TYPE = NONE for hardware_clk. (constraint file d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 4).
Applied set_property KEEP_HIERARCHY = SOFT for pll. (constraint file auto generated constraint).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 1584.652 ; gain = 716.773
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:18 . Memory (MB): peak = 1584.652 ; gain = 716.773
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:01:29 . Memory (MB): peak = 1578.020 ; gain = 710.027
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics
@@ -173,7 +173,7 @@ DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elapsed = 00:00:40 . Memory (MB): peak = 1584.652 ; gain = 716.773
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:03:07 . Memory (MB): peak = 1578.020 ; gain = 710.027
---------------------------------------------------------------------------------
Sort Area is CPU__GC0 alu/result0_0 : 0 0 : 3101 5879 : Used 1 time 0
Sort Area is CPU__GC0 alu/result0_0 : 0 1 : 2778 5879 : Used 1 time 0
@@ -183,6 +183,14 @@ Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:06 ; elaps
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
ROM: Preliminary Mapping Report
+------------------+-------------+---------------+----------------+
|Module Name | RTL Object | Depth x Width | Implemented As |
+------------------+-------------+---------------+----------------+
|InstructionMemory | instruction | 256x32 | LUT |
+------------------+-------------+---------------+----------------+
DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |
@@ -201,19 +209,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:47 . Memory (MB): peak = 1584.652 ; gain = 716.773
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:03:21 . Memory (MB): peak = 1578.020 ; gain = 710.027
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:10 ; elapsed = 00:00:56 . Memory (MB): peak = 1761.211 ; gain = 893.332
Finished Timing Optimization : Time (s): cpu = 00:00:44 ; elapsed = 00:03:49 . Memory (MB): peak = 1712.805 ; gain = 844.812
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:12 ; elapsed = 00:01:02 . Memory (MB): peak = 1767.527 ; gain = 899.648
Finished Technology Mapping : Time (s): cpu = 00:00:45 ; elapsed = 00:04:00 . Memory (MB): peak = 1719.152 ; gain = 851.160
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
@@ -231,37 +239,37 @@ Start Final Netlist Cleanup
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:12 ; elapsed = 00:01:06 . Memory (MB): peak = 1767.527 ; gain = 899.648
Finished IO Insertion : Time (s): cpu = 00:00:46 ; elapsed = 00:04:09 . Memory (MB): peak = 1719.152 ; gain = 851.160
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:12 ; elapsed = 00:01:06 . Memory (MB): peak = 1767.527 ; gain = 899.648
Finished Renaming Generated Instances : Time (s): cpu = 00:00:46 ; elapsed = 00:04:09 . Memory (MB): peak = 1719.152 ; gain = 851.160
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648
Finished Renaming Generated Ports : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648
Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648
Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
@@ -291,40 +299,41 @@ Report Cell Usage:
|1 |phase_locked_loop | 1|
|2 |CARRY4 | 39|
|3 |DSP48E1 | 3|
|4 |LUT1 | 2|
|5 |LUT2 | 183|
|6 |LUT3 | 231|
|7 |LUT4 | 300|
|8 |LUT5 | 720|
|9 |LUT6 | 6947|
|10 |MUXF7 | 2426|
|4 |LUT1 | 15|
|5 |LUT2 | 155|
|6 |LUT3 | 229|
|7 |LUT4 | 279|
|8 |LUT5 | 831|
|9 |LUT6 | 7147|
|10 |MUXF7 | 2373|
|11 |MUXF8 | 1088|
|12 |FDRE | 18118|
|13 |IBUF | 1|
|14 |OBUF | 13|
|12 |FDRE | 17752|
|13 |FDSE | 368|
|14 |IBUF | 1|
|15 |OBUF | 13|
+------+------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648
Finished Writing Synthesis Report : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:12 ; elapsed = 00:01:05 . Memory (MB): peak = 1767.527 ; gain = 791.645
Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:01:08 . Memory (MB): peak = 1767.527 ; gain = 899.648
Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:03:58 . Memory (MB): peak = 1719.152 ; gain = 751.750
Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.245 . Memory (MB): peak = 1767.527 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 3556 Unisim elements for replacement
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1724.391 ; gain = 0.000
INFO: [Netlist 29-17] Analyzing 3503 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1767.527 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1729.113 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Synth Design complete | Checksum: a3f3fba1
Synth Design complete | Checksum: 93dc575b
INFO: [Common 17-83] Releasing license: Synthesis
51 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:13 ; elapsed = 00:01:15 . Memory (MB): peak = 1767.527 ; gain = 1293.230
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1767.527 ; gain = 0.000
synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:04:35 . Memory (MB): peak = 1729.113 ; gain = 1252.605
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1729.113 ; gain = 0.000
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 21:04:53 2024...
INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 14:27:28 2024...

BIN
PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb
View File

Binary file not shown.

33
PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt
View File

@@ -1,7 +1,7 @@
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
| Date : Fri Jul 12 21:04:53 2024
| Date : Sat Jul 13 14:27:28 2024
| Host : Viviana running 64-bit major release (build 9200)
| Command : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
| Design : CPU
@@ -31,13 +31,13 @@ Table of Contents
+-------------------------+-------+-------+------------+-----------+-------+
| Site Type | Used | Fixed | Prohibited | Available | Util% |
+-------------------------+-------+-------+------------+-----------+-------+
| Slice LUTs* | 8042 | 0 | 0 | 20800 | 38.66 |
| LUT as Logic | 8042 | 0 | 0 | 20800 | 38.66 |
| Slice LUTs* | 8380 | 0 | 0 | 20800 | 40.29 |
| LUT as Logic | 8380 | 0 | 0 | 20800 | 40.29 |
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
| Slice Registers | 18118 | 0 | 0 | 41600 | 43.55 |
| Register as Flip Flop | 18118 | 0 | 0 | 41600 | 43.55 |
| Slice Registers | 18120 | 0 | 0 | 41600 | 43.56 |
| Register as Flip Flop | 18120 | 0 | 0 | 41600 | 43.56 |
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
| F7 Muxes | 2426 | 0 | 0 | 16300 | 14.88 |
| F7 Muxes | 2373 | 0 | 0 | 16300 | 14.56 |
| F8 Muxes | 1088 | 0 | 0 | 8150 | 13.35 |
+-------------------------+-------+-------+------------+-----------+-------+
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
@@ -58,8 +58,8 @@ Warning! LUT value is adjusted to account for LUT combining.
| 0 | Yes | - | - |
| 0 | Yes | - | Set |
| 0 | Yes | - | Reset |
| 0 | Yes | Set | - |
| 18118 | Yes | Reset | - |
| 368 | Yes | Set | - |
| 17752 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
@@ -152,18 +152,19 @@ Warning! LUT value is adjusted to account for LUT combining.
+----------+-------+---------------------+
| Ref Name | Used | Functional Category |
+----------+-------+---------------------+
| FDRE | 18118 | Flop & Latch |
| LUT6 | 6947 | LUT |
| MUXF7 | 2426 | MuxFx |
| FDRE | 17752 | Flop & Latch |
| LUT6 | 7147 | LUT |
| MUXF7 | 2373 | MuxFx |
| MUXF8 | 1088 | MuxFx |
| LUT5 | 720 | LUT |
| LUT4 | 300 | LUT |
| LUT3 | 231 | LUT |
| LUT2 | 183 | LUT |
| LUT5 | 831 | LUT |
| FDSE | 368 | Flop & Latch |
| LUT4 | 279 | LUT |
| LUT3 | 229 | LUT |
| LUT2 | 155 | LUT |
| CARRY4 | 39 | CarryLogic |
| LUT1 | 15 | LUT |
| OBUF | 13 | IO |
| DSP48E1 | 3 | Block Arithmetic |
| LUT1 | 2 | LUT |
| IBUF | 1 | IO |
+----------+-------+---------------------+

4
PipelineProcessor.runs/synth_1/vivado.jou
View File

@@ -3,8 +3,8 @@
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
# Start of session at: Fri Jul 12 21:03:30 2024
# Process ID: 19744
# Start of session at: Sat Jul 13 14:22:20 2024
# Process ID: 3472
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1
# Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds

BIN
PipelineProcessor.runs/synth_1/vivado.pb
View File

Binary file not shown.