Fix stack initialization

2024-07-14 00:06:05 +08:00
parent 43ce61daf9
commit f00725e8f3
43 changed files with 2895 additions and 2873 deletions
--- a/PipelineProcessor.runs/impl_1/CPU.tcl
+++ b/PipelineProcessor.runs/impl_1/CPU.tcl
@@ -123,7 +123,6 @@ set ACTIVE_STEP init_design
 set rc [catch {
  create_msg_db init_design.pb
  set_param chipscope.maxJobs 5
  set_param xicom.use_bs_reader 1
  set_param runs.launchOptions { -jobs 20  }
 OPTRACE "create in-memory project" START { }
  create_project -in_memory -part xc7a35tfgg484-1
--- a/PipelineProcessor.runs/impl_1/CPU.vdi
+++ b/PipelineProcessor.runs/impl_1/CPU.vdi
@@ -3,8 +3,8 @@
 # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
-# Start of session at: Sat Jul 13 14:27:36 2024
+# Start of session at: Sat Jul 13 23:39:15 2024
-# Process ID: 19592
+# Process ID: 27020
 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1
 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
 # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi
@@ -12,14 +12,14 @@
 # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
 #-----------------------------------------------------------
 source CPU.tcl -notrace
-create_project: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 462.727 ; gain = 184.750
+create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 461.707 ; gain = 184.406
 Command: link_design -top CPU -part xc7a35tfgg484-1
 Design is defaulting to srcset: sources_1
 Design is defaulting to constrset: constrs_1
 INFO: [Device 21-403] Loading part xc7a35tfgg484-1
 INFO: [Project 1-454] Reading design checkpoint 'd:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp' for cell 'pll'
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.175 . Memory (MB): peak = 915.922 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.154 . Memory (MB): peak = 916.031 ; gain = 0.000
-INFO: [Netlist 29-17] Analyzing 3504 Unisim elements for replacement
+INFO: [Netlist 29-17] Analyzing 3508 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-479] Netlist was created with Vivado 2023.2
 INFO: [Project 1-570] Preparing netlist for logic optimization
@@ -28,18 +28,18 @@ Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/Pipelin
 Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
 INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
 INFO: [Timing 38-2] Deriving generated clocks [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc:54]
-get_clocks: Time (s): cpu = 00:00:02 ; elapsed = 00:00:09 . Memory (MB): peak = 1598.910 ; gain = 559.754
+get_clocks: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1599.215 ; gain = 558.836
 Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'pll/inst'
 Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
 Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/constrs_1/new/top.xdc]
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1598.910 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1599.215 ; gain = 0.000
 INFO: [Project 1-111] Unisim Transformation Summary:
 No Unisim elements were transformed.
 10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
 link_design completed successfully
-link_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 1598.910 ; gain = 1122.715
+link_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 1599.215 ; gain = 1122.352
 Command: opt_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
 INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
@@ -50,112 +50,112 @@ INFO: [DRC 23-27] Running DRC with 2 threads
 INFO: [Project 1-461] DRC finished with 0 Errors
 INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1598.910 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.715 . Memory (MB): peak = 1599.215 ; gain = 0.000
 Starting Cache Timing Information Task
 INFO: [Timing 38-35] Done setting XDC timing constraints.
-Ending Cache Timing Information Task | Checksum: 144775da6
+Ending Cache Timing Information Task | Checksum: 1f0fa50d6
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.821 . Memory (MB): peak = 1613.023 ; gain = 14.113
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.490 . Memory (MB): peak = 1613.043 ; gain = 13.828
 Starting Logic Optimization Task
 Phase 1 Initialization
 Phase 1.1 Core Generation And Design Setup
-Phase 1.1 Core Generation And Design Setup | Checksum: 144775da6
+Phase 1.1 Core Generation And Design Setup | Checksum: 1f0fa50d6
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Phase 1.2 Setup Constraints And Sort Netlist
-Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 144775da6
+Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1f0fa50d6
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.011 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Phase 1 Initialization | Checksum: 144775da6
+Phase 1 Initialization | Checksum: 1f0fa50d6
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Phase 2 Timer Update And Timing Data Collection
 Phase 2.1 Timer Update
-Phase 2.1 Timer Update | Checksum: 144775da6
+Phase 2.1 Timer Update | Checksum: 1f0fa50d6
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.617 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.387 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Phase 2.2 Timing Data Collection
-Phase 2.2 Timing Data Collection | Checksum: 144775da6
+Phase 2.2 Timing Data Collection | Checksum: 1f0fa50d6
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.640 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.405 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Phase 2 Timer Update And Timing Data Collection | Checksum: 144775da6
+Phase 2 Timer Update And Timing Data Collection | Checksum: 1f0fa50d6
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.642 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.407 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Phase 3 Retarget
 INFO: [Opt 31-1566] Pulled 13 inverters resulting in an inversion of 263 pins
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
 INFO: [Opt 31-49] Retargeted 0 cell(s).
-Phase 3 Retarget | Checksum: 17395c2ed
+Phase 3 Retarget | Checksum: 1e587632b
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.901 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.567 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Retarget | Checksum: 17395c2ed
+Retarget | Checksum: 1e587632b
 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 14 cells
 INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 
 Phase 4 Constant propagation
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Phase 4 Constant propagation | Checksum: 1c089ccf4
+Phase 4 Constant propagation | Checksum: 1b5603850
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.652 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Constant propagation | Checksum: 1c089ccf4
+Constant propagation | Checksum: 1b5603850
 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
 Phase 5 Sweep
-Phase 5 Sweep | Checksum: 12eb909f8
+Phase 5 Sweep | Checksum: 15ea6b1a3
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.816 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Sweep | Checksum: 12eb909f8
+Sweep | Checksum: 15ea6b1a3
 INFO: [Opt 31-389] Phase Sweep created 12 cells and removed 0 cells
 Phase 6 BUFG optimization
-Phase 6 BUFG optimization | Checksum: 12eb909f8
+Phase 6 BUFG optimization | Checksum: 15ea6b1a3
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.949 . Memory (MB): peak = 1972.328 ; gain = 0.000
-BUFG optimization | Checksum: 12eb909f8
+BUFG optimization | Checksum: 15ea6b1a3
 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
 Phase 7 Shift Register Optimization
 INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
-Phase 7 Shift Register Optimization | Checksum: 12eb909f8
+Phase 7 Shift Register Optimization | Checksum: 15ea6b1a3
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.959 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Shift Register Optimization | Checksum: 12eb909f8
+Shift Register Optimization | Checksum: 15ea6b1a3
 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
 Phase 8 Post Processing Netlist
-Phase 8 Post Processing Netlist | Checksum: 17562fe4e
+Phase 8 Post Processing Netlist | Checksum: 118407d59
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.991 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Post Processing Netlist | Checksum: 17562fe4e
+Post Processing Netlist | Checksum: 118407d59
 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
 Phase 9 Finalization
 Phase 9.1 Finalizing Design Cores and Updating Shapes
-Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1329e1c39
+Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 1587ffb16
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Phase 9.2 Verifying Netlist Connectivity
 Starting Connectivity Check Task
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Phase 9.2 Verifying Netlist Connectivity | Checksum: 1329e1c39
+Phase 9.2 Verifying Netlist Connectivity | Checksum: 1587ffb16
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Phase 9 Finalization | Checksum: 1329e1c39
+Phase 9 Finalization | Checksum: 1587ffb16
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Opt_design Change Summary
 =========================
@@ -172,32 +172,31 @@ Opt_design Change Summary
 -------------------------------------------------------------------------------------------------------------------------
-Ending Logic Optimization Task | Checksum: 1329e1c39
+Ending Logic Optimization Task | Checksum: 1587ffb16
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
-Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Starting Power Optimization Task
 INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
-Ending Power Optimization Task | Checksum: 1329e1c39
+Ending Power Optimization Task | Checksum: 1587ffb16
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Starting Final Cleanup Task
-Ending Final Cleanup Task | Checksum: 1329e1c39
+Ending Final Cleanup Task | Checksum: 1587ffb16
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Starting Netlist Obfuscation Task
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Ending Netlist Obfuscation Task | Checksum: 1329e1c39
+Ending Netlist Obfuscation Task | Checksum: 1587ffb16
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 1972.328 ; gain = 0.000
 INFO: [Common 17-83] Releasing license: Implementation
 30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
 opt_design completed successfully
 opt_design: Time (s): cpu = 00:00:01 ; elapsed = 00:00:08 . Memory (MB): peak = 1972.844 ; gain = 373.934
 INFO: [runtcl-4] Executing : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
 Command: report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -205,16 +204,16 @@ INFO: [DRC 23-27] Running DRC with 2 threads
 INFO: [Vivado_Tcl 2-168] The results of DRC are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt.
 report_drc completed successfully
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Writing XDEF routing.
 Writing XDEF routing logical nets.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.022 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.045 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.066 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 1972.328 ; gain = 0.000
 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_opt.dcp' has been generated.
 Command: place_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -234,59 +233,59 @@ Starting Placer Task
 Phase 1 Placer Initialization
 Phase 1.1 Placer Initialization Netlist Sorting
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.008 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 9a573811
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 14ae9822c
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.012 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1972.328 ; gain = 0.000
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
 INFO: [Timing 38-35] Done setting XDC timing constraints.
-Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 161645cda
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: b434b971
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.844 ; gain = 0.000
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 1972.328 ; gain = 0.000
 Phase 1.3 Build Placer Netlist Model
-Phase 1.3 Build Placer Netlist Model | Checksum: 254135206
+Phase 1.3 Build Placer Netlist Model | Checksum: c5c27cdb
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 1.4 Constrain Clocks/Macros
-Phase 1.4 Constrain Clocks/Macros | Checksum: 254135206
+Phase 1.4 Constrain Clocks/Macros | Checksum: c5c27cdb
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297
-Phase 1 Placer Initialization | Checksum: 254135206
+Phase 1 Placer Initialization | Checksum: c5c27cdb
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:04 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 2 Global Placement
 Phase 2.1 Floorplanning
-Phase 2.1 Floorplanning | Checksum: 21edfd7da
+Phase 2.1 Floorplanning | Checksum: 146e69098
-Time (s): cpu = 00:00:02 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 2.2 Update Timing before SLR Path Opt
-Phase 2.2 Update Timing before SLR Path Opt | Checksum: 187f6e72f
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 151ff6269
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 2.3 Post-Processing in Floorplanning
-Phase 2.3 Post-Processing in Floorplanning | Checksum: 187f6e72f
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 151ff6269
-Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:05 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 2.4 Global Placement Core
 Phase 2.4.1 UpdateTiming Before Physical Synthesis
-Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 2bcb2d97a
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: a33c0039
-Time (s): cpu = 00:00:06 ; elapsed = 00:00:12 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:12 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 2.4.2 Physical Synthesis In Placer
-INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 61 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 55 LUT instances to create LUTNM shape
 INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
-INFO: [Physopt 32-1138] End 1 Pass. Optimized 29 nets or LUTs. Breaked 0 LUT, combined 29 existing LUTs and moved 0 existing LUT
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 25 nets or LUTs. Breaked 0 LUT, combined 25 existing LUTs and moved 0 existing LUT
 INFO: [Physopt 32-65] No nets found for high-fanout optimization.
 INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
 INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
@@ -297,7 +296,7 @@ INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was
 INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
 INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
 INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 2040.230 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 2039.625 ; gain = 0.000
 Summary of Physical Synthesis Optimizations
 ============================================
@@ -306,7 +305,7 @@ Summary of Physical Synthesis Optimizations
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
 |  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
-|  LUT Combining                                    |            0  |             29  |                    29  |           0  |           1  |  00:00:00  |
+|  LUT Combining                                    |            0  |             25  |                    25  |           0  |           1  |  00:00:00  |
 |  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
 |  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
 |  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
@@ -315,59 +314,59 @@ Summary of Physical Synthesis Optimizations
 |  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
 |  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
-|  Total                                            |            0  |             29  |                    29  |           0  |           4  |  00:00:00  |
+|  Total                                            |            0  |             25  |                    25  |           0  |           4  |  00:00:00  |
 -----------------------------------------------------------------------------------------------------------------------------------------------------------
-Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1cd490dfe
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: f4053bc8
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297
-Phase 2.4 Global Placement Core | Checksum: 2593ef06b
+Phase 2.4 Global Placement Core | Checksum: 1099bb7b7
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297
-Phase 2 Global Placement | Checksum: 2593ef06b
+Phase 2 Global Placement | Checksum: 1099bb7b7
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:13 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:13 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 3 Detail Placement
 Phase 3.1 Commit Multi Column Macros
-Phase 3.1 Commit Multi Column Macros | Checksum: 24c2e5196
+Phase 3.1 Commit Multi Column Macros | Checksum: 10f07ac64
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:14 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 3.2 Commit Most Macros & LUTRAMs
-Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1b29cdebe
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 1626a5454
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:15 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 3.3 Area Swap Optimization
-Phase 3.3 Area Swap Optimization | Checksum: 1fd1f47c3
+Phase 3.3 Area Swap Optimization | Checksum: 14fc2b59e
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 3.4 Pipeline Register Optimization
-Phase 3.4 Pipeline Register Optimization | Checksum: 1bbf6b047
+Phase 3.4 Pipeline Register Optimization | Checksum: 169ab9d86
-Time (s): cpu = 00:00:07 ; elapsed = 00:00:16 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 3.5 Small Shape Detail Placement
-Phase 3.5 Small Shape Detail Placement | Checksum: 1f0217d20
+Phase 3.5 Small Shape Detail Placement | Checksum: 10a431286
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:26 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 3.6 Re-assign LUT pins
-Phase 3.6 Re-assign LUT pins | Checksum: 149d47d39
+Phase 3.6 Re-assign LUT pins | Checksum: 145095dfd
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 3.7 Pipeline Register Optimization
-Phase 3.7 Pipeline Register Optimization | Checksum: 14f4d2963
+Phase 3.7 Pipeline Register Optimization | Checksum: 1b6341a4b
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297
-Phase 3 Detail Placement | Checksum: 14f4d2963
+Phase 3 Detail Placement | Checksum: 1b6341a4b
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:27 . Memory (MB): peak = 2040.230 ; gain = 67.387
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:26 . Memory (MB): peak = 2039.625 ; gain = 67.297
 Phase 4 Post Placement Optimization and Clean-Up
@@ -375,7 +374,7 @@ Phase 4.1 Post Commit Optimization
 INFO: [Timing 38-35] Done setting XDC timing constraints.
 Phase 4.1.1 Post Placement Optimization
-Post Placement Optimization Initialization | Checksum: 1b9a7b723
+Post Placement Optimization Initialization | Checksum: 253ce2c5c
 Phase 4.1.1.1 BUFG Insertion
@@ -383,34 +382,34 @@ Starting Physical Synthesis Task
 Phase 1 Physical Synthesis Initialization
 INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
-INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.040 | TNS=0.000 |
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.979 | TNS=0.000 |
-Phase 1 Physical Synthesis Initialization | Checksum: 19276cbb6
+Phase 1 Physical Synthesis Initialization | Checksum: 16956e8df
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.744 . Memory (MB): peak = 2088.574 ; gain = 13.941
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.808 . Memory (MB): peak = 2085.480 ; gain = 13.727
 INFO: [Place 46-33] Processed net data_memory/reset, BUFG insertion was skipped due to placement/routing conflicts.
 INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
-Ending Physical Synthesis Task | Checksum: 19276cbb6
+Ending Physical Synthesis Task | Checksum: 16956e8df
-Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2090.840 ; gain = 16.207
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2087.383 ; gain = 15.629
-Phase 4.1.1.1 BUFG Insertion | Checksum: 1b9a7b723
+Phase 4.1.1.1 BUFG Insertion | Checksum: 253ce2c5c
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
 Phase 4.1.1.2 Post Placement Timing Optimization
-INFO: [Place 30-746] Post Placement Timing Summary WNS=2.040. For the most accurate timing information please run report_timing.
+INFO: [Place 30-746] Post Placement Timing Summary WNS=2.979. For the most accurate timing information please run report_timing.
-Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1b853f6e8
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1e8b73056
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
-Phase 4.1 Post Commit Optimization | Checksum: 1b853f6e8
+Phase 4.1 Post Commit Optimization | Checksum: 1e8b73056
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:32 . Memory (MB): peak = 2090.840 ; gain = 117.996
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
 Phase 4.2 Post Placement Cleanup
-Phase 4.2 Post Placement Cleanup | Checksum: 1b853f6e8
+Phase 4.2 Post Placement Cleanup | Checksum: 1e8b73056
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
 Phase 4.3 Placer Reporting
@@ -420,51 +419,51 @@ INFO: [Place 30-612] Post-Placement Estimated Congestion
 |           | Global Congestion | Short Congestion  |
 | Direction | Region Size       | Region Size       |
 |___________|___________________|___________________|
-|      North|                4x4|                2x2|
+|      North|                2x2|                1x1|
 |___________|___________________|___________________|
-|      South|                1x1|                1x1|
+|      South|                1x1|                2x2|
 |___________|___________________|___________________|
 |       East|                1x1|                1x1|
 |___________|___________________|___________________|
 |       West|                1x1|                1x1|
 |___________|___________________|___________________|
-Phase 4.3.1 Print Estimated Congestion | Checksum: 1b853f6e8
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1e8b73056
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
-Phase 4.3 Placer Reporting | Checksum: 1b853f6e8
+Phase 4.3 Placer Reporting | Checksum: 1e8b73056
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
 Phase 4.4 Final Placement Cleanup
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.021 . Memory (MB): peak = 2091.523 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2087.383 ; gain = 0.000
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
-Phase 4 Post Placement Optimization and Clean-Up | Checksum: 10fcc6d31
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11ee518f9
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
-Ending Placer Task | Checksum: 51a85dd7
+Ending Placer Task | Checksum: 91ee5898
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:32 . Memory (MB): peak = 2091.523 ; gain = 118.680
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:32 . Memory (MB): peak = 2087.383 ; gain = 115.055
 66 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
 place_design completed successfully
-place_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:33 . Memory (MB): peak = 2091.523 ; gain = 118.680
+place_design: Time (s): cpu = 00:00:04 ; elapsed = 00:00:33 . Memory (MB): peak = 2087.383 ; gain = 115.055
 INFO: [runtcl-4] Executing : report_io -file CPU_io_placed.rpt
-report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.048 . Memory (MB): peak = 2091.523 ; gain = 0.000
+report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 2087.383 ; gain = 0.000
 INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
 INFO: [runtcl-4] Executing : report_control_sets -verbose -file CPU_control_sets_placed.rpt
-report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 2091.523 ; gain = 0.000
+report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.065 . Memory (MB): peak = 2087.383 ; gain = 0.000
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.023 . Memory (MB): peak = 2106.918 ; gain = 1.973
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.028 . Memory (MB): peak = 2105.285 ; gain = 2.945
-Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2106.918 ; gain = 0.000
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2105.285 ; gain = 2.945
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2106.918 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2105.285 ; gain = 0.000
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2106.918 ; gain = 0.000
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2105.285 ; gain = 0.000
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 2106.918 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.041 . Memory (MB): peak = 2105.285 ; gain = 0.000
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2106.918 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2105.285 ; gain = 0.000
-Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2106.918 ; gain = 1.973
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2105.285 ; gain = 2.945
 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_placed.dcp' has been generated.
 Command: phys_opt_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -472,23 +471,23 @@ INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc
 Starting Initial Update Timing Task
-Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2153.953 ; gain = 47.035
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:03 . Memory (MB): peak = 2150.406 ; gain = 45.121
 INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
 INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
 INFO: [Common 17-83] Releasing license: Implementation
 75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
 phys_opt_design completed successfully
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.025 . Memory (MB): peak = 2179.293 ; gain = 7.062
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2175.750 ; gain = 7.027
-Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2179.293 ; gain = 7.062
+Wrote PlaceDB: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2177.184 ; gain = 1.434
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2179.293 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2177.184 ; gain = 0.000
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2179.293 ; gain = 0.000
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 2177.184 ; gain = 0.000
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.039 . Memory (MB): peak = 2179.293 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.033 . Memory (MB): peak = 2177.184 ; gain = 0.000
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2179.293 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 2177.184 ; gain = 0.000
-Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2179.293 ; gain = 7.062
+Write Physdb Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 2177.184 ; gain = 8.461
 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_physopt.dcp' has been generated.
 Command: route_design
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -503,30 +502,30 @@ Starting Routing Task
 INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
 Phase 1 Build RT Design
-Checksum: PlaceDB: 4fa4d64c ConstDB: 0 ShapeSum: 203878b RouteDB: 0
+Checksum: PlaceDB: 7d4dfd1d ConstDB: 0 ShapeSum: 14a05b7b RouteDB: 0
-Post Restoration Checksum: NetGraph: c8a283dc | NumContArr: aad6ec74 | Constraints: c2a8fa9d | Timing: c2a8fa9d
+Post Restoration Checksum: NetGraph: 678b964f | NumContArr: 2f28cab3 | Constraints: c2a8fa9d | Timing: c2a8fa9d
-Phase 1 Build RT Design | Checksum: 2f8cb658a
+Phase 1 Build RT Design | Checksum: 21c06563c
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391
 Phase 2 Router Initialization
 Phase 2.1 Fix Topology Constraints
-Phase 2.1 Fix Topology Constraints | Checksum: 2f8cb658a
+Phase 2.1 Fix Topology Constraints | Checksum: 21c06563c
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391
 Phase 2.2 Pre Route Cleanup
-Phase 2.2 Pre Route Cleanup | Checksum: 2f8cb658a
+Phase 2.2 Pre Route Cleanup | Checksum: 21c06563c
-Time (s): cpu = 00:00:09 ; elapsed = 00:00:13 . Memory (MB): peak = 2289.805 ; gain = 79.008
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 2288.059 ; gain = 82.391
 Number of Nodes with overlaps = 0
 Phase 2.3 Update Timing
-Phase 2.3 Update Timing | Checksum: 201a59748
+Phase 2.3 Update Timing | Checksum: 30afab1eb
-Time (s): cpu = 00:00:12 ; elapsed = 00:00:17 . Memory (MB): peak = 2307.527 ; gain = 96.730
+Time (s): cpu = 00:00:02 ; elapsed = 00:00:18 . Memory (MB): peak = 2305.797 ; gain = 100.129
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.230  | TNS=0.000  | WHS=-0.144 | THS=-28.052|
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.232  | TNS=0.000  | WHS=-0.150 | THS=-18.367|
 Router Utilization Summary
@@ -535,93 +534,93 @@ Router Utilization Summary
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
-  Number of Failed Nets               = 21997
+  Number of Failed Nets               = 22010
    (Failed Nets is the sum of unrouted and partially routed nets)
-  Number of Unrouted Nets             = 21997
+  Number of Unrouted Nets             = 22010
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0
-Phase 2 Router Initialization | Checksum: 276df3972
+Phase 2 Router Initialization | Checksum: 3338dbc90
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2345.027 ; gain = 134.230
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.363 ; gain = 141.695
 Phase 3 Initial Routing
 Phase 3.1 Global Routing
-Phase 3.1 Global Routing | Checksum: 276df3972
+Phase 3.1 Global Routing | Checksum: 3338dbc90
-Time (s): cpu = 00:00:13 ; elapsed = 00:00:19 . Memory (MB): peak = 2345.027 ; gain = 134.230
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:20 . Memory (MB): peak = 2347.363 ; gain = 141.695
 Phase 3.2 Initial Net Routing
-Phase 3.2 Initial Net Routing | Checksum: 1646cdf4d
+Phase 3.2 Initial Net Routing | Checksum: 18b5441e3
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 2349.422 ; gain = 138.625
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 2348.094 ; gain = 142.426
-Phase 3 Initial Routing | Checksum: 1646cdf4d
+Phase 3 Initial Routing | Checksum: 18b5441e3
-Time (s): cpu = 00:00:14 ; elapsed = 00:00:20 . Memory (MB): peak = 2349.422 ; gain = 138.625
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:21 . Memory (MB): peak = 2348.094 ; gain = 142.426
 Phase 4 Rip-up And Reroute
 Phase 4.1 Global Iteration 0
- Number of Nodes with overlaps = 3178
+ Number of Nodes with overlaps = 3428
- Number of Nodes with overlaps = 255
+ Number of Nodes with overlaps = 278
- Number of Nodes with overlaps = 41
+ Number of Nodes with overlaps = 35
 Number of Nodes with overlaps = 12
- Number of Nodes with overlaps = 2
+ Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 0
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537  | TNS=0.000  | WHS=N/A    | THS=N/A    |
-Phase 4.1 Global Iteration 0 | Checksum: 3741328e8
+Phase 4.1 Global Iteration 0 | Checksum: 2a3342fb1
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:31 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.875 ; gain = 147.207
-Phase 4 Rip-up And Reroute | Checksum: 3741328e8
+Phase 4 Rip-up And Reroute | Checksum: 2a3342fb1
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:31 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.875 ; gain = 147.207
 Phase 5 Delay and Skew Optimization
 Phase 5.1 Delay CleanUp
 Phase 5.1.1 Update Timing
-Phase 5.1.1 Update Timing | Checksum: 2b9958991
+Phase 5.1.1 Update Timing | Checksum: 294396ac7
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.879 ; gain = 147.211
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679  | TNS=0.000  | WHS=N/A    | THS=N/A    |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537  | TNS=0.000  | WHS=N/A    | THS=N/A    |
-Phase 5.1 Delay CleanUp | Checksum: 2b9958991
+Phase 5.1 Delay CleanUp | Checksum: 294396ac7
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.879 ; gain = 147.211
 Phase 5.2 Clock Skew Optimization
-Phase 5.2 Clock Skew Optimization | Checksum: 2b9958991
+Phase 5.2 Clock Skew Optimization | Checksum: 294396ac7
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2352.879 ; gain = 147.211
-Phase 5 Delay and Skew Optimization | Checksum: 2b9958991
+Phase 5 Delay and Skew Optimization | Checksum: 294396ac7
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:32 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:34 . Memory (MB): peak = 2352.879 ; gain = 147.211
 Phase 6 Post Hold Fix
 Phase 6.1 Hold Fix Iter
 Phase 6.1.1 Update Timing
-Phase 6.1.1 Update Timing | Checksum: 2903d569b
+Phase 6.1.1 Update Timing | Checksum: 26ed22ad4
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211
-INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.679  | TNS=0.000  | WHS=0.070  | THS=0.000  |
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.537  | TNS=0.000  | WHS=0.055  | THS=0.000  |
-Phase 6.1 Hold Fix Iter | Checksum: 2ecebe266
+Phase 6.1 Hold Fix Iter | Checksum: 26dd53850
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211
-Phase 6 Post Hold Fix | Checksum: 2ecebe266
+Phase 6 Post Hold Fix | Checksum: 26dd53850
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211
 Phase 7 Route finalize
 Router Utilization Summary
-  Global Vertical Routing Utilization    = 16.0809 %
+  Global Vertical Routing Utilization    = 15.1075 %
-  Global Horizontal Routing Utilization  = 14.8794 %
+  Global Horizontal Routing Utilization  = 15.2186 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
@@ -631,44 +630,44 @@ Router Utilization Summary
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0
-Phase 7 Route finalize | Checksum: 2ecebe266
+Phase 7 Route finalize | Checksum: 26dd53850
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2352.559 ; gain = 141.762
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2352.879 ; gain = 147.211
 Phase 8 Verifying routed nets
 Verification completed successfully
-Phase 8 Verifying routed nets | Checksum: 2ecebe266
+Phase 8 Verifying routed nets | Checksum: 26dd53850
-Time (s): cpu = 00:00:19 ; elapsed = 00:00:33 . Memory (MB): peak = 2354.578 ; gain = 143.781
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.930 ; gain = 149.262
 Phase 9 Depositing Routes
-Phase 9 Depositing Routes | Checksum: 2aa639e35
+Phase 9 Depositing Routes | Checksum: 1e498ff47
-Time (s): cpu = 00:00:20 ; elapsed = 00:00:34 . Memory (MB): peak = 2354.578 ; gain = 143.781
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.930 ; gain = 149.262
 Phase 10 Post Router Timing
-INFO: [Route 35-57] Estimated Timing Summary | WNS=2.679  | TNS=0.000  | WHS=0.070  | THS=0.000  |
+INFO: [Route 35-57] Estimated Timing Summary | WNS=3.537  | TNS=0.000  | WHS=0.055  | THS=0.000  |
 INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
-Phase 10 Post Router Timing | Checksum: 2aa639e35
+Phase 10 Post Router Timing | Checksum: 1e498ff47
-Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:36 . Memory (MB): peak = 2354.930 ; gain = 149.262
 INFO: [Route 35-16] Router Completed Successfully
 Phase 11 Post-Route Event Processing
-Phase 11 Post-Route Event Processing | Checksum: 6f450aed
+Phase 11 Post-Route Event Processing | Checksum: 118a89fd7
-Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:37 . Memory (MB): peak = 2354.930 ; gain = 149.262
-Ending Routing Task | Checksum: 6f450aed
+Ending Routing Task | Checksum: 118a89fd7
-Time (s): cpu = 00:00:20 ; elapsed = 00:00:35 . Memory (MB): peak = 2354.578 ; gain = 143.781
+Time (s): cpu = 00:00:07 ; elapsed = 00:00:37 . Memory (MB): peak = 2354.930 ; gain = 149.262
 Routing Is Done.
 INFO: [Common 17-83] Releasing license: Implementation
 90 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
 route_design completed successfully
-route_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:36 . Memory (MB): peak = 2354.578 ; gain = 175.285
+route_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:38 . Memory (MB): peak = 2354.930 ; gain = 177.746
 INFO: [runtcl-4] Executing : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
 Command: report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
 INFO: [IP_Flow 19-1839] IP Catalog is up to date.
@@ -681,7 +680,7 @@ INFO: [Timing 38-35] Done setting XDC timing constraints.
 INFO: [DRC 23-133] Running Methodology with 2 threads
 INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt.
 report_methodology completed successfully
-report_methodology: Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 2435.902 ; gain = 81.324
+report_methodology: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 2436.516 ; gain = 81.586
 INFO: [runtcl-4] Executing : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
 Command: report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
 INFO: [Timing 38-35] Done setting XDC timing constraints.
@@ -701,16 +700,16 @@ INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file CPU_bus_sk
 INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
 INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
 INFO: [Timing 38-480] Writing timing data to binary archive.
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.034 . Memory (MB): peak = 2496.238 ; gain = 3.922
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.031 . Memory (MB): peak = 2498.938 ; gain = 4.973
-Wrote PlaceDB: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2497.543 ; gain = 1.305
+Wrote PlaceDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:01 . Memory (MB): peak = 2499.391 ; gain = 0.453
-Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2497.543 ; gain = 0.000
+Wrote PulsedLatchDB: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2499.391 ; gain = 0.000
 Writing XDEF routing.
 Writing XDEF routing logical nets.
 Writing XDEF routing special nets.
-Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.221 . Memory (MB): peak = 2497.543 ; gain = 0.000
+Wrote RouteStorage: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.230 . Memory (MB): peak = 2499.391 ; gain = 0.000
-Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.026 . Memory (MB): peak = 2497.543 ; gain = 0.000
+Wrote Netlist Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.036 . Memory (MB): peak = 2499.391 ; gain = 0.000
-Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2497.543 ; gain = 0.000
+Wrote Device Cache: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 2499.391 ; gain = 0.000
-Write Physdb Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2497.543 ; gain = 5.227
+Write Physdb Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:02 . Memory (MB): peak = 2499.391 ; gain = 5.426
 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU_routed.dcp' has been generated.
 Command: write_bitstream -force CPU.bit
 Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
@@ -754,5 +753,5 @@ INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT dev
 INFO: [Common 17-83] Releasing license: Implementation
 14 Infos, 13 Warnings, 0 Critical Warnings and 0 Errors encountered.
 write_bitstream completed successfully
-write_bitstream: Time (s): cpu = 00:00:08 ; elapsed = 00:00:12 . Memory (MB): peak = 2966.875 ; gain = 469.332
+write_bitstream: Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 2964.719 ; gain = 465.328
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 14:30:07 2024...
+INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 23:41:35 2024...
--- a/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_bus_skew_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-| Date         : Sat Jul 13 14:29:52 2024
+| Date         : Sat Jul 13 23:41:19 2024
 | Host         : Viviana running 64-bit major release  (build 9200)
 | Command      : report_bus_skew -warn_on_violation -file CPU_bus_skew_routed.rpt -pb CPU_bus_skew_routed.pb -rpx CPU_bus_skew_routed.rpx
 | Design       : CPU
--- a/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_clock_utilization_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-| Date         : Sat Jul 13 14:29:52 2024
+| Date         : Sat Jul 13 23:41:19 2024
 | Host         : Viviana running 64-bit major release  (build 9200)
 | Command      : report_clock_utilization -file CPU_clock_utilization_routed.rpt
 | Design       : CPU
@@ -78,12 +78,12 @@ Table of Contents
 +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
 | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
 +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
-| X0Y0              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 1517 |  1200 |  460 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X0Y0              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 3068 |  1200 |  988 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
-| X1Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    1 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 3911 |  1500 | 1072 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X1Y0              |    2 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    1 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 4193 |  1500 | 1239 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
-| X0Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 2799 |  1200 |  937 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X0Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 2689 |  1200 |  887 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
-| X1Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 3610 |  1500 | 1055 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
+| X1Y1              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 3944 |  1500 | 1126 |   450 |    0 |    40 |    0 |    20 |    0 |    20 |
-| X0Y2              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 4277 |  1800 |  774 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
+| X0Y2              |    1 |    12 |    0 |     4 |    0 |     2 |    0 |     4 |    0 |     1 |    0 |     1 |    0 |     0 |    0 |     0 |    0 |    50 |    0 |    50 | 3420 |  1800 |  711 |   400 |    0 |    20 |    0 |    10 |    0 |    20 |
-| X1Y2              |    1 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 | 2018 |   950 |  601 |   300 |    0 |    10 |    0 |     5 |    0 |    20 |
+| X1Y2              |    1 |    12 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     0 |    0 |     4 |    0 |     1 |    0 |     0 |    0 |     0 |  818 |   950 |  246 |   300 |    0 |    10 |    0 |     5 |    0 |    20 |
 +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
 * Global Clock column represents track count; while other columns represents cell counts
@@ -118,9 +118,9 @@ All Modules
 +----+-------+-------+-----------------------+
 |    | X0    | X1    | HORIZONTAL PROG DELAY |
 +----+-------+-------+-----------------------+
-| Y2 |  4277 |  2018 |                     0 |
+| Y2 |  3420 |   818 |                     0 |
-| Y1 |  2799 |  3610 |                     0 |
+| Y1 |  2689 |  3944 |                     0 |
-| Y0 |  1517 |  3911 |                     0 |
+| Y0 |  3068 |  4193 |                     0 |
 +----+-------+-------+-----------------------+
@@ -153,7 +153,7 @@ All Modules
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
 | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net               |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
-| g0        | n/a   | BUFG/O          | None       |        1517 |               0 | 1517 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
+| g0        | n/a   | BUFG/O          | None       |        3068 |               0 | 3068 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
 * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
 ** Non-Clock Loads column represents cell count of non-clock pin loads
@@ -166,7 +166,7 @@ All Modules
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
 | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net                                     |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
-| g0        | n/a   | BUFG/O          | None       |        3911 |               0 | 3911 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1                       |
+| g0        | n/a   | BUFG/O          | None       |        4193 |               0 | 4193 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1                       |
 | g1        | n/a   | BUFG/O          | None       |           1 |               0 |    0 |           0 |    0 |   0 |  0 |    0 |   1 |       0 | pll/inst/clkfbout_buf_phase_locked_loop |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-----------------------------------------+
 * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
@@ -180,7 +180,7 @@ All Modules
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
 | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net               |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
-| g0        | n/a   | BUFG/O          | None       |        2799 |               0 | 2799 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
+| g0        | n/a   | BUFG/O          | None       |        2689 |               0 | 2689 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
 * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
 ** Non-Clock Loads column represents cell count of non-clock pin loads
@@ -193,7 +193,7 @@ All Modules
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
 | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net               |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
-| g0        | n/a   | BUFG/O          | None       |        3610 |               0 | 3610 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
+| g0        | n/a   | BUFG/O          | None       |        3944 |               0 | 3944 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
 * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
 ** Non-Clock Loads column represents cell count of non-clock pin loads
@@ -206,7 +206,7 @@ All Modules
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
 | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net               |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
-| g0        | n/a   | BUFG/O          | None       |        4277 |               0 | 4277 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
+| g0        | n/a   | BUFG/O          | None       |        3420 |               0 | 3420 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
 +-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
 * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
 ** Non-Clock Loads column represents cell count of non-clock pin loads
@@ -216,11 +216,11 @@ All Modules
 13. Clock Region Cell Placement per Global Clock: Region X1Y2
 -------------------------------------------------------------
-+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------------+
-| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF   | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net               |
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF  | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net               |
-+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------------+
-| g0        | n/a   | BUFG/O          | None       |        2018 |               0 | 2018 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
+| g0        | n/a   | BUFG/O          | None       |         818 |               0 | 818 |           0 |    0 |   0 |  0 |    0 |   0 |       0 | pll/inst/clk_out1 |
-+-----------+-------+-----------------+------------+-------------+-----------------+------+-------------+------+-----+----+------+-----+---------+-------------------+
+-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+-------------------+
 * Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
 ** Non-Clock Loads column represents cell count of non-clock pin loads
 *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
--- a/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_control_sets_placed.rpt
--- a/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_drc_opted.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-| Date         : Sat Jul 13 14:28:18 2024
+| Date         : Sat Jul 13 23:39:42 2024
 | Host         : Viviana running 64-bit major release  (build 9200)
 | Command      : report_drc -file CPU_drc_opted.rpt -pb CPU_drc_opted.pb -rpx CPU_drc_opted.rpx
 | Design       : CPU
--- a/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_drc_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-| Date         : Sat Jul 13 14:29:40 2024
+| Date         : Sat Jul 13 23:41:07 2024
 | Host         : Viviana running 64-bit major release  (build 9200)
 | Command      : report_drc -file CPU_drc_routed.rpt -pb CPU_drc_routed.pb -rpx CPU_drc_routed.rpx
 | Design       : CPU
--- a/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_io_placed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 ----------------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version              : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-| Date                      : Sat Jul 13 14:28:53 2024
+| Date                      : Sat Jul 13 23:40:16 2024
 | Host                      : Viviana running 64-bit major release  (build 9200)
 | Command                   : report_io -file CPU_io_placed.rpt
 | Design                    : CPU
--- a/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_methodology_drc_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 -----------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-| Date         : Sat Jul 13 14:29:46 2024
+| Date         : Sat Jul 13 23:41:13 2024
 | Host         : Viviana running 64-bit major release  (build 9200)
 | Command      : report_methodology -file CPU_methodology_drc_routed.rpt -pb CPU_methodology_drc_routed.pb -rpx CPU_methodology_drc_routed.rpx
 | Design       : CPU
--- a/PipelineProcessor.runs/impl_1/CPU_opt.dcp
+++ b/PipelineProcessor.runs/impl_1/CPU_opt.dcp
--- a/PipelineProcessor.runs/impl_1/CPU_physopt.dcp
+++ b/PipelineProcessor.runs/impl_1/CPU_physopt.dcp
--- a/PipelineProcessor.runs/impl_1/CPU_placed.dcp
+++ b/PipelineProcessor.runs/impl_1/CPU_placed.dcp
--- a/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_power_routed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 -------------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version     : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-| Date             : Sat Jul 13 14:29:51 2024
+| Date             : Sat Jul 13 23:41:18 2024
 | Host             : Viviana running 64-bit major release  (build 9200)
 | Command          : report_power -file CPU_power_routed.rpt -pb CPU_power_summary_routed.pb -rpx CPU_power_routed.rpx
 | Design           : CPU
@@ -30,10 +30,10 @@ Table of Contents
 ----------
 +--------------------------+--------------+
-| Total On-Chip Power (W)  | 0.189        |
+| Total On-Chip Power (W)  | 0.188        |
 | Design Power Budget (W)  | Unspecified* |
 | Power Budget Margin (W)  | NA           |
-| Dynamic (W)              | 0.120        |
+| Dynamic (W)              | 0.119        |
 | Device Static (W)        | 0.069        |
 | Effective TJA (C/W)      | 2.8          |
 | Max Ambient (C)          | 84.5         |
@@ -52,19 +52,19 @@ Table of Contents
 +----------------+-----------+----------+-----------+-----------------+
 | On-Chip        | Power (W) | Used     | Available | Utilization (%) |
 +----------------+-----------+----------+-----------+-----------------+
-| Clocks         |     0.016 |        5 |       --- |             --- |
+| Clocks         |     0.015 |        5 |       --- |             --- |
-| Slice Logic    |     0.003 |    30286 |       --- |             --- |
+| Slice Logic    |     0.003 |    30293 |       --- |             --- |
-|   LUT as Logic |     0.003 |     8337 |     20800 |           40.08 |
+|   LUT as Logic |     0.003 |     8344 |     20800 |           40.12 |
 |   CARRY4       |    <0.001 |       39 |      8150 |            0.48 |
 |   Register     |    <0.001 |    18132 |     41600 |           43.59 |
-|   F7/F8 Muxes  |    <0.001 |     3461 |     32600 |           10.62 |
+|   F7/F8 Muxes  |    <0.001 |     3465 |     32600 |           10.63 |
 |   Others       |     0.000 |       12 |       --- |             --- |
-| Signals        |     0.002 |    21997 |       --- |             --- |
+| Signals        |     0.002 |    22010 |       --- |             --- |
 | PLL            |     0.099 |        1 |         5 |           20.00 |
 | DSPs           |    <0.001 |        3 |        90 |            3.33 |
 | I/O            |    <0.001 |       15 |       250 |            6.00 |
 | Static Power   |     0.069 |          |           |                 |
-| Total          |     0.189 |          |           |                 |
+| Total          |     0.188 |          |           |                 |
 +----------------+-----------+----------+-----------+-----------------+
@@ -74,7 +74,7 @@ Table of Contents
 +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
 | Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
 +-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
-| Vccint    |       1.000 |     0.040 |       0.030 |      0.010 |       NA    | Unspecified | NA         |
+| Vccint    |       1.000 |     0.038 |       0.029 |      0.010 |       NA    | Unspecified | NA         |
 | Vccaux    |       1.800 |     0.063 |       0.050 |      0.013 |       NA    | Unspecified | NA         |
 | Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
 | Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
@@ -145,10 +145,9 @@ Table of Contents
 +----------------------+-----------+
 | Name                 | Power (W) |
 +----------------------+-----------+
-| CPU                  |     0.120 |
+| CPU                  |     0.119 |
-|   data_memory        |     0.014 |
+|   data_memory        |     0.013 |
 |   instruction_decode |     0.002 |
 |     register_file    |     0.001 |
 |   instruction_fetch  |     0.001 |
 |   pll                |     0.100 |
 |     inst             |     0.100 |
--- a/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb
+++ b/PipelineProcessor.runs/impl_1/CPU_power_summary_routed.pb
--- a/PipelineProcessor.runs/impl_1/CPU_route_status.pb
+++ b/PipelineProcessor.runs/impl_1/CPU_route_status.pb
--- a/PipelineProcessor.runs/impl_1/CPU_route_status.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_route_status.rpt
@@ -1,11 +1,11 @@
 Design Route Status
                                               :      # nets :
   ------------------------------------------- : ----------- :
-   # of logical nets.......................... :       30511 :
+   # of logical nets.......................... :       30518 :
-       # of nets not needing routing.......... :        8507 :
+       # of nets not needing routing.......... :        8501 :
-           # of internally routed nets........ :        8507 :
+           # of internally routed nets........ :        8501 :
-       # of routable nets..................... :       22004 :
+       # of routable nets..................... :       22017 :
-           # of fully routed nets............. :       22004 :
+           # of fully routed nets............. :       22017 :
       # of nets with routing errors.......... :           0 :
   ------------------------------------------- : ----------- :
--- a/PipelineProcessor.runs/impl_1/CPU_routed.dcp
+++ b/PipelineProcessor.runs/impl_1/CPU_routed.dcp
--- a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb
+++ b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.pb
--- a/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_timing_summary_routed.rpt
--- a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb
+++ b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.pb
--- a/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt
+++ b/PipelineProcessor.runs/impl_1/CPU_utilization_placed.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-| Date         : Sat Jul 13 14:28:53 2024
+| Date         : Sat Jul 13 23:40:17 2024
 | Host         : Viviana running 64-bit major release  (build 9200)
 | Command      : report_utilization -file CPU_utilization_placed.rpt -pb CPU_utilization_placed.pb
 | Design       : CPU
@@ -32,13 +32,13 @@ Table of Contents
 +-------------------------+-------+-------+------------+-----------+-------+
 |        Site Type        |  Used | Fixed | Prohibited | Available | Util% |
 +-------------------------+-------+-------+------------+-----------+-------+
-| Slice LUTs              |  8337 |     0 |          0 |     20800 | 40.08 |
+| Slice LUTs              |  8344 |     0 |          0 |     20800 | 40.12 |
-|   LUT as Logic          |  8337 |     0 |          0 |     20800 | 40.08 |
+|   LUT as Logic          |  8344 |     0 |          0 |     20800 | 40.12 |
 |   LUT as Memory         |     0 |     0 |          0 |      9600 |  0.00 |
 | Slice Registers         | 18132 |     0 |          0 |     41600 | 43.59 |
 |   Register as Flip Flop | 18132 |     0 |          0 |     41600 | 43.59 |
 |   Register as Latch     |     0 |     0 |          0 |     41600 |  0.00 |
-| F7 Muxes                |  2373 |     0 |          0 |     16300 | 14.56 |
+| F7 Muxes                |  2377 |     0 |          0 |     16300 | 14.58 |
 | F8 Muxes                |  1088 |     0 |          0 |      8150 | 13.35 |
 +-------------------------+-------+-------+------------+-----------+-------+
 * Warning! LUT value is adjusted to account for LUT combining.
@@ -69,21 +69,21 @@ Table of Contents
 +--------------------------------------------+-------+-------+------------+-----------+-------+
 |                  Site Type                 |  Used | Fixed | Prohibited | Available | Util% |
 +--------------------------------------------+-------+-------+------------+-----------+-------+
-| Slice                                      |  7477 |     0 |          0 |      8150 | 91.74 |
+| Slice                                      |  7058 |     0 |          0 |      8150 | 86.60 |
-|   SLICEL                                   |  5277 |     0 |            |           |       |
+|   SLICEL                                   |  4944 |     0 |            |           |       |
-|   SLICEM                                   |  2200 |     0 |            |           |       |
+|   SLICEM                                   |  2114 |     0 |            |           |       |
-| LUT as Logic                               |  8337 |     0 |          0 |     20800 | 40.08 |
+| LUT as Logic                               |  8344 |     0 |          0 |     20800 | 40.12 |
 |   using O5 output only                     |     0 |       |            |           |       |
-|   using O6 output only                     |  8032 |       |            |           |       |
+|   using O6 output only                     |  8043 |       |            |           |       |
-|   using O5 and O6                          |   305 |       |            |           |       |
+|   using O5 and O6                          |   301 |       |            |           |       |
 | LUT as Memory                              |     0 |     0 |          0 |      9600 |  0.00 |
 |   LUT as Distributed RAM                   |     0 |     0 |            |           |       |
 |   LUT as Shift Register                    |     0 |     0 |            |           |       |
 | Slice Registers                            | 18132 |     0 |          0 |     41600 | 43.59 |
-|   Register driven from within the Slice    |  1478 |       |            |           |       |
+|   Register driven from within the Slice    |  1461 |       |            |           |       |
-|   Register driven from outside the Slice   | 16654 |       |            |           |       |
+|   Register driven from outside the Slice   | 16671 |       |            |           |       |
-|     LUT in front of the register is unused | 14681 |       |            |           |       |
+|     LUT in front of the register is unused | 14188 |       |            |           |       |
-|     LUT in front of the register is used   |  1973 |       |            |           |       |
+|     LUT in front of the register is used   |  2483 |       |            |           |       |
 | Unique Control Sets                        |   547 |       |          0 |      8150 |  6.71 |
 +--------------------------------------------+-------+-------+------------+-----------+-------+
 * * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
@@ -181,14 +181,14 @@ Table of Contents
 |  Ref Name |  Used | Functional Category |
 +-----------+-------+---------------------+
 | FDRE      | 17764 |        Flop & Latch |
-| LUT6      |  7147 |                 LUT |
+| LUT6      |  7154 |                 LUT |
-| MUXF7     |  2373 |               MuxFx |
+| MUXF7     |  2377 |               MuxFx |
 | MUXF8     |  1088 |               MuxFx |
-| LUT5      |   831 |                 LUT |
+| LUT5      |   825 |                 LUT |
 | FDSE      |   368 |        Flop & Latch |
-| LUT4      |   279 |                 LUT |
+| LUT4      |   281 |                 LUT |
-| LUT3      |   229 |                 LUT |
+| LUT3      |   230 |                 LUT |
-| LUT2      |   155 |                 LUT |
+| LUT2      |   154 |                 LUT |
 | CARRY4    |    39 |          CarryLogic |
 | OBUF      |    13 |                  IO |
 | DSP48E1   |     3 |    Block Arithmetic |
--- a/PipelineProcessor.runs/impl_1/clockInfo.txt
+++ b/PipelineProcessor.runs/impl_1/clockInfo.txt
@@ -1,6 +1,6 @@
 -------------------------------------
 | Tool Version : Vivado v.2023.2
-| Date         : Sat Jul 13 14:28:25 2024
+| Date         : Sat Jul 13 23:39:48 2024
 | Host         : Viviana
 | Design       : design_1
 | Device       : xc7a35t-fgg484-1--
--- a/PipelineProcessor.runs/impl_1/init_design.pb
+++ b/PipelineProcessor.runs/impl_1/init_design.pb
--- a/PipelineProcessor.runs/impl_1/opt_design.pb
+++ b/PipelineProcessor.runs/impl_1/opt_design.pb
--- a/PipelineProcessor.runs/impl_1/phys_opt_design.pb
+++ b/PipelineProcessor.runs/impl_1/phys_opt_design.pb
--- a/PipelineProcessor.runs/impl_1/place_design.pb
+++ b/PipelineProcessor.runs/impl_1/place_design.pb
--- a/PipelineProcessor.runs/impl_1/route_design.pb
+++ b/PipelineProcessor.runs/impl_1/route_design.pb
--- a/PipelineProcessor.runs/impl_1/vivado.jou
+++ b/PipelineProcessor.runs/impl_1/vivado.jou
@@ -3,8 +3,8 @@
 # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
-# Start of session at: Sat Jul 13 14:27:36 2024
+# Start of session at: Sat Jul 13 23:39:15 2024
-# Process ID: 19592
+# Process ID: 27020
 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1
 # Command line: vivado.exe -log CPU.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source CPU.tcl -notrace
 # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/impl_1/CPU.vdi
--- a/PipelineProcessor.runs/impl_1/vivado.pb
+++ b/PipelineProcessor.runs/impl_1/vivado.pb
--- a/PipelineProcessor.runs/impl_1/write_bitstream.pb
+++ b/PipelineProcessor.runs/impl_1/write_bitstream.pb
--- a/PipelineProcessor.runs/synth_1/CPU.dcp
+++ b/PipelineProcessor.runs/synth_1/CPU.dcp
--- a/PipelineProcessor.runs/synth_1/CPU.tcl
+++ b/PipelineProcessor.runs/synth_1/CPU.tcl
@@ -71,7 +71,6 @@ proc create_report { reportName command } {
 }
 OPTRACE "synth_1" START { ROLLUP_AUTO }
 set_param chipscope.maxJobs 5
 set_param xicom.use_bs_reader 1
 OPTRACE "Creating in-memory project" START { }
 create_project -in_memory -part xc7a35tfgg484-1
--- a/PipelineProcessor.runs/synth_1/CPU.vds
+++ b/PipelineProcessor.runs/synth_1/CPU.vds
@@ -3,8 +3,8 @@
 # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
-# Start of session at: Sat Jul 13 14:22:20 2024
+# Start of session at: Sat Jul 13 23:37:30 2024
-# Process ID: 3472
+# Process ID: 27796
 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1
 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
 # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds
@@ -12,7 +12,7 @@
 # Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
 #-----------------------------------------------------------
 source CPU.tcl -notrace
-create_project: Time (s): cpu = 00:00:05 ; elapsed = 00:00:22 . Memory (MB): peak = 463.508 ; gain = 184.387
+create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:05 . Memory (MB): peak = 462.984 ; gain = 184.277
 Command: read_checkpoint -auto_incremental -incremental D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
 INFO: [Vivado 12-5825] Read reference checkpoint from D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp for incremental synthesis
 INFO: [Vivado 12-7989] Please ensure there are no constraint changes
@@ -25,13 +25,13 @@ INFO: [Designutils 20-5440] No compile time benefit to using incremental synthes
 INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
 INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
-INFO: [Synth 8-7075] Helper process launched with PID 30200
+INFO: [Synth 8-7075] Helper process launched with PID 15424
 ---------------------------------------------------------------------------------
-Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:18 . Memory (MB): peak = 1308.621 ; gain = 440.629
+Starting RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:04 . Memory (MB): peak = 1308.293 ; gain = 439.242
 ---------------------------------------------------------------------------------
 INFO: [Synth 8-6157] synthesizing module 'CPU' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/CPU.v:2]
-INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-3472-Viviana/realtime/phase_locked_loop_stub.v:6]
+INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-27796-Viviana/realtime/phase_locked_loop_stub.v:6]
-INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-3472-Viviana/realtime/phase_locked_loop_stub.v:6]
+INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/.Xil/Vivado-27796-Viviana/realtime/phase_locked_loop_stub.v:6]
 INFO: [Synth 8-6157] synthesizing module 'InstFetch' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstFetch.v:2]
 INFO: [Synth 8-6157] synthesizing module 'InstructionMemory' [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
 INFO: [Synth 8-6155] done synthesizing module 'InstructionMemory' (0#1) [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v:3]
@@ -66,18 +66,18 @@ WARNING: [Synth 8-7129] Port address[0] in module DataMemory is either unconnect
 WARNING: [Synth 8-7129] Port address[1] in module InstructionMemory is either unconnected or has no load
 WARNING: [Synth 8-7129] Port address[0] in module InstructionMemory is either unconnected or has no load
 ---------------------------------------------------------------------------------
-Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617
+Finished RTL Elaboration : Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 1478.973 ; gain = 609.922
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1478.973 ; gain = 609.922
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:30 . Memory (MB): peak = 1478.609 ; gain = 610.617
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:00 ; elapsed = 00:00:07 . Memory (MB): peak = 1478.973 ; gain = 609.922
 ---------------------------------------------------------------------------------
-Netlist sorting complete. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.793 . Memory (MB): peak = 1478.609 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.191 . Memory (MB): peak = 1478.973 ; gain = 0.000
 INFO: [Project 1-570] Preparing netlist for logic optimization
 Processing XDC Constraints
@@ -90,22 +90,22 @@ INFO: [Project 1-236] Implementation specific constraints were found while readi
 Resolution: To avoid this warning, move constraints listed in [.Xil/CPU_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
 Completed Processing XDC Constraints
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.010 . Memory (MB): peak = 1578.020 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 1586.277 ; gain = 0.000
 INFO: [Project 1-111] Unisim Transformation Summary:
 No Unisim elements were transformed.
-Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.243 . Memory (MB): peak = 1578.020 ; gain = 0.000
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.069 . Memory (MB): peak = 1586.277 ; gain = 0.000
 INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
 INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
 ---------------------------------------------------------------------------------
-Finished Constraint Validation : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027
+Finished Constraint Validation : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Loading Part and Timing Information
 ---------------------------------------------------------------------------------
 Loading part: xc7a35tfgg484-1
 ---------------------------------------------------------------------------------
-Finished Loading Part and Timing Information : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Applying 'set_property' XDC Constraints
@@ -114,10 +114,10 @@ Applied set_property IO_BUFFER_TYPE = NONE for hardware_clk. (constraint file  d
 Applied set_property CLOCK_BUFFER_TYPE = NONE for hardware_clk. (constraint file  d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop/phase_locked_loop_in_context.xdc, line 4).
 Applied set_property KEEP_HIERARCHY = SOFT for pll. (constraint file  auto generated constraint).
 ---------------------------------------------------------------------------------
-Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:13 ; elapsed = 00:01:07 . Memory (MB): peak = 1578.020 ; gain = 710.027
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:01 ; elapsed = 00:00:17 . Memory (MB): peak = 1586.277 ; gain = 717.227
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:17 ; elapsed = 00:01:29 . Memory (MB): peak = 1578.020 ; gain = 710.027
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:01 ; elapsed = 00:00:22 . Memory (MB): peak = 1586.277 ; gain = 717.227
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start RTL Component Statistics 
@@ -173,7 +173,7 @@ DSP Report: Generating DSP alu/result0, operation Mode is: (PCIN>>17)+A*B.
 DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
 DSP Report: operator alu/result0 is absorbed into DSP alu/result0.
 ---------------------------------------------------------------------------------
-Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:37 ; elapsed = 00:03:07 . Memory (MB): peak = 1578.020 ; gain = 710.027
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:00:44 . Memory (MB): peak = 1586.277 ; gain = 717.227
 ---------------------------------------------------------------------------------
 Sort Area is CPU__GC0 alu/result0_0 : 0 0 : 3101 5879 : Used 1 time 0
 Sort Area is CPU__GC0 alu/result0_0 : 0 1 : 2778 5879 : Used 1 time 0
@@ -209,19 +209,19 @@ Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
 Start Applying XDC Timing Constraints
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:39 ; elapsed = 00:03:21 . Memory (MB): peak = 1578.020 ; gain = 710.027
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:02 ; elapsed = 00:00:51 . Memory (MB): peak = 1586.277 ; gain = 717.227
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Timing Optimization
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Timing Optimization : Time (s): cpu = 00:00:44 ; elapsed = 00:03:49 . Memory (MB): peak = 1712.805 ; gain = 844.812
+Finished Timing Optimization : Time (s): cpu = 00:00:02 ; elapsed = 00:01:07 . Memory (MB): peak = 1714.559 ; gain = 845.508
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Technology Mapping
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Technology Mapping : Time (s): cpu = 00:00:45 ; elapsed = 00:04:00 . Memory (MB): peak = 1719.152 ; gain = 851.160
+Finished Technology Mapping : Time (s): cpu = 00:00:02 ; elapsed = 00:01:14 . Memory (MB): peak = 1720.918 ; gain = 851.867
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start IO Insertion
@@ -239,37 +239,37 @@ Start Final Netlist Cleanup
 Finished Final Netlist Cleanup
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished IO Insertion : Time (s): cpu = 00:00:46 ; elapsed = 00:04:09 . Memory (MB): peak = 1719.152 ; gain = 851.160
+Finished IO Insertion : Time (s): cpu = 00:00:03 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.918 ; gain = 851.867
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Instances
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Instances : Time (s): cpu = 00:00:46 ; elapsed = 00:04:09 . Memory (MB): peak = 1719.152 ; gain = 851.160
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:03 ; elapsed = 00:01:19 . Memory (MB): peak = 1720.918 ; gain = 851.867
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Rebuilding User Hierarchy
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Ports
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Ports : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Handling Custom Attributes
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Handling Custom Attributes : Time (s): cpu = 00:00:46 ; elapsed = 00:04:12 . Memory (MB): peak = 1719.152 ; gain = 851.160
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Renaming Generated Nets
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
-Finished Renaming Generated Nets : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
 ---------------------------------------------------------------------------------
 ---------------------------------------------------------------------------------
 Start Writing Synthesis Report
@@ -300,12 +300,12 @@ Report Cell Usage:
 |2     |CARRY4            |    39|
 |3     |DSP48E1           |     3|
 |4     |LUT1              |    15|
-|5     |LUT2              |   155|
+|5     |LUT2              |   154|
-|6     |LUT3              |   229|
+|6     |LUT3              |   230|
-|7     |LUT4              |   279|
+|7     |LUT4              |   281|
-|8     |LUT5              |   831|
+|8     |LUT5              |   825|
-|9     |LUT6              |  7147|
+|9     |LUT6              |  7154|
-|10    |MUXF7             |  2373|
+|10    |MUXF7             |  2377|
 |11    |MUXF8             |  1088|
 |12    |FDRE              | 17752|
 |13    |FDSE              |   368|
@@ -313,27 +313,27 @@ Report Cell Usage:
 |15    |OBUF              |    13|
 +------+------------------+------+
 ---------------------------------------------------------------------------------
-Finished Writing Synthesis Report : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:03 ; elapsed = 00:01:21 . Memory (MB): peak = 1720.918 ; gain = 851.867
 ---------------------------------------------------------------------------------
 Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
-Synthesis Optimization Runtime : Time (s): cpu = 00:00:37 ; elapsed = 00:03:58 . Memory (MB): peak = 1719.152 ; gain = 751.750
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:03 ; elapsed = 00:01:18 . Memory (MB): peak = 1720.918 ; gain = 744.562
-Synthesis Optimization Complete : Time (s): cpu = 00:00:46 ; elapsed = 00:04:13 . Memory (MB): peak = 1719.152 ; gain = 851.160
+Synthesis Optimization Complete : Time (s): cpu = 00:00:03 ; elapsed = 00:01:22 . Memory (MB): peak = 1720.918 ; gain = 851.867
 INFO: [Project 1-571] Translating synthesized netlist
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.429 . Memory (MB): peak = 1724.391 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.294 . Memory (MB): peak = 1720.918 ; gain = 0.000
-INFO: [Netlist 29-17] Analyzing 3503 Unisim elements for replacement
+INFO: [Netlist 29-17] Analyzing 3507 Unisim elements for replacement
 INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
 INFO: [Project 1-570] Preparing netlist for logic optimization
 INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
-Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.015 . Memory (MB): peak = 1729.113 ; gain = 0.000
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.005 . Memory (MB): peak = 1720.918 ; gain = 0.000
 INFO: [Project 1-111] Unisim Transformation Summary:
 No Unisim elements were transformed.
-Synth Design complete | Checksum: 93dc575b
+Synth Design complete | Checksum: 560bc728
 INFO: [Common 17-83] Releasing license: Synthesis
 51 Infos, 5 Warnings, 0 Critical Warnings and 0 Errors encountered.
 synth_design completed successfully
-synth_design: Time (s): cpu = 00:00:51 ; elapsed = 00:04:35 . Memory (MB): peak = 1729.113 ; gain = 1252.605
+synth_design: Time (s): cpu = 00:00:03 ; elapsed = 00:01:29 . Memory (MB): peak = 1720.918 ; gain = 1244.781
-Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.029 . Memory (MB): peak = 1729.113 ; gain = 0.000
+Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1720.918 ; gain = 0.000
 INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.dcp' has been generated.
 INFO: [runtcl-4] Executing : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
-INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 14:27:28 2024...
+INFO: [Common 17-206] Exiting Vivado at Sat Jul 13 23:39:08 2024...
--- a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb
+++ b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.pb
--- a/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt
+++ b/PipelineProcessor.runs/synth_1/CPU_utilization_synth.rpt
@@ -1,7 +1,7 @@
 Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
 ---------------------------------------------------------------------------------------------------------------------------------------------
 | Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
-| Date         : Sat Jul 13 14:27:28 2024
+| Date         : Sat Jul 13 23:39:08 2024
 | Host         : Viviana running 64-bit major release  (build 9200)
 | Command      : report_utilization -file CPU_utilization_synth.rpt -pb CPU_utilization_synth.pb
 | Design       : CPU
@@ -31,13 +31,13 @@ Table of Contents
 +-------------------------+-------+-------+------------+-----------+-------+
 |        Site Type        |  Used | Fixed | Prohibited | Available | Util% |
 +-------------------------+-------+-------+------------+-----------+-------+
-| Slice LUTs*             |  8380 |     0 |          0 |     20800 | 40.29 |
+| Slice LUTs*             |  8384 |     0 |          0 |     20800 | 40.31 |
-|   LUT as Logic          |  8380 |     0 |          0 |     20800 | 40.29 |
+|   LUT as Logic          |  8384 |     0 |          0 |     20800 | 40.31 |
 |   LUT as Memory         |     0 |     0 |          0 |      9600 |  0.00 |
 | Slice Registers         | 18120 |     0 |          0 |     41600 | 43.56 |
 |   Register as Flip Flop | 18120 |     0 |          0 |     41600 | 43.56 |
 |   Register as Latch     |     0 |     0 |          0 |     41600 |  0.00 |
-| F7 Muxes                |  2373 |     0 |          0 |     16300 | 14.56 |
+| F7 Muxes                |  2377 |     0 |          0 |     16300 | 14.58 |
 | F8 Muxes                |  1088 |     0 |          0 |      8150 | 13.35 |
 +-------------------------+-------+-------+------------+-----------+-------+
 * Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
@@ -153,14 +153,14 @@ Warning! LUT value is adjusted to account for LUT combining.
 | Ref Name |  Used | Functional Category |
 +----------+-------+---------------------+
 | FDRE     | 17752 |        Flop & Latch |
-| LUT6     |  7147 |                 LUT |
+| LUT6     |  7154 |                 LUT |
-| MUXF7    |  2373 |               MuxFx |
+| MUXF7    |  2377 |               MuxFx |
 | MUXF8    |  1088 |               MuxFx |
-| LUT5     |   831 |                 LUT |
+| LUT5     |   825 |                 LUT |
 | FDSE     |   368 |        Flop & Latch |
-| LUT4     |   279 |                 LUT |
+| LUT4     |   281 |                 LUT |
-| LUT3     |   229 |                 LUT |
+| LUT3     |   230 |                 LUT |
-| LUT2     |   155 |                 LUT |
+| LUT2     |   154 |                 LUT |
 | CARRY4   |    39 |          CarryLogic |
 | LUT1     |    15 |                 LUT |
 | OBUF     |    13 |                  IO |
--- a/PipelineProcessor.runs/synth_1/vivado.jou
+++ b/PipelineProcessor.runs/synth_1/vivado.jou
@@ -3,8 +3,8 @@
 # SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
 # IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
 # SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
-# Start of session at: Sat Jul 13 14:22:20 2024
+# Start of session at: Sat Jul 13 23:37:30 2024
-# Process ID: 3472
+# Process ID: 27796
 # Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1
 # Command line: vivado.exe -log CPU.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source CPU.tcl
 # Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/synth_1/CPU.vds
--- a/PipelineProcessor.runs/synth_1/vivado.pb
+++ b/PipelineProcessor.runs/synth_1/vivado.pb
--- a/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb
+++ b/PipelineProcessor.sim/sim_1/behav/xsim/xelab.pb
--- a/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
+++ b/PipelineProcessor.sim/sim_1/behav/xsim/xsim.dir/test_cpu_behav/xsim.mem
--- a/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb
+++ b/PipelineProcessor.sim/sim_1/behav/xsim/xvlog.pb
--- a/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
+++ b/PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
@@ -8,7 +8,7 @@ module InstructionMemory (
    always @(*) begin
        case (address[31:2])
            20'd0:   instruction <= 32'h3c1d4000;
-            20'd1:   instruction <= 32'h23bd07ff;
+            20'd1:   instruction <= 32'h23bd07fc;
            20'd2:   instruction <= 32'h3c104000;
            20'd3:   instruction <= 32'h22100020;
            20'd4:   instruction <= 32'h2011003f;
@@ -43,174 +43,173 @@ module InstructionMemory (
            20'd33:  instruction <= 32'hae110038;
            20'd34:  instruction <= 32'h20110071;
            20'd35:  instruction <= 32'hae11003c;
-            20'd36:  instruction <= 32'h0c00002a;
+            20'd36:  instruction <= 32'h3c084000;
-            20'd37:  instruction <= 32'h3c084000;
+            20'd37:  instruction <= 32'h8d040060;
-            20'd38:  instruction <= 32'h8d040060;
+            20'd38:  instruction <= 32'h0c000076;
-            20'd39:  instruction <= 32'h0c000077;
+            20'd39:  instruction <= 32'h0c000029;
-            20'd40:  instruction <= 32'h0c00002a;
+            20'd40:  instruction <= 32'h08000027;
-            20'd41:  instruction <= 32'h08000028;
+            20'd41:  instruction <= 32'h23bdffec;
-            20'd42:  instruction <= 32'h23bdffec;
+            20'd42:  instruction <= 32'hafbf0004;
-            20'd43:  instruction <= 32'hafbf0004;
+            20'd43:  instruction <= 32'hafb00008;
-            20'd44:  instruction <= 32'hafb00008;
+            20'd44:  instruction <= 32'hafb1000c;
-            20'd45:  instruction <= 32'hafb1000c;
+            20'd45:  instruction <= 32'hafb20010;
-            20'd46:  instruction <= 32'hafb20010;
+            20'd46:  instruction <= 32'hafb30014;
-            20'd47:  instruction <= 32'hafb30014;
+            20'd47:  instruction <= 32'h3c104000;
-            20'd48:  instruction <= 32'h3c104000;
+            20'd48:  instruction <= 32'h22110010;
-            20'd49:  instruction <= 32'h22110010;
+            20'd49:  instruction <= 32'h22100060;
-            20'd50:  instruction <= 32'h22100060;
+            20'd50:  instruction <= 32'h20120000;
-            20'd51:  instruction <= 32'h20120000;
+            20'd51:  instruction <= 32'h8e130000;
-            20'd52:  instruction <= 32'h8e130000;
+            20'd52:  instruction <= 32'h22100004;
-            20'd53:  instruction <= 32'h22100004;
+            20'd53:  instruction <= 32'h00124080;
-            20'd54:  instruction <= 32'h00124080;
+            20'd54:  instruction <= 32'h02084020;
-            20'd55:  instruction <= 32'h02084020;
+            20'd55:  instruction <= 32'h8d040000;
-            20'd56:  instruction <= 32'h8d040000;
+            20'd56:  instruction <= 32'h22250000;
-            20'd57:  instruction <= 32'h22250000;
+            20'd57:  instruction <= 32'h0c000045;
-            20'd58:  instruction <= 32'h0c000046;
+            20'd58:  instruction <= 32'h22520001;
-            20'd59:  instruction <= 32'h22520001;
+            20'd59:  instruction <= 32'h02724022;
-            20'd60:  instruction <= 32'h02724022;
+            20'd60:  instruction <= 32'h1d00fff8;
-            20'd61:  instruction <= 32'h1d00fff8;
+            20'd61:  instruction <= 32'h0c00006f;
-            20'd62:  instruction <= 32'h0c000070;
+            20'd62:  instruction <= 32'h8fbf0004;
-            20'd63:  instruction <= 32'h8fbf0004;
+            20'd63:  instruction <= 32'h8fb00008;
-            20'd64:  instruction <= 32'h8fb00008;
+            20'd64:  instruction <= 32'h8fb1000c;
-            20'd65:  instruction <= 32'h8fb1000c;
+            20'd65:  instruction <= 32'h8fb20010;
-            20'd66:  instruction <= 32'h8fb20010;
+            20'd66:  instruction <= 32'h8fb30014;
-            20'd67:  instruction <= 32'h8fb30014;
+            20'd67:  instruction <= 32'h23bd0014;
-            20'd68:  instruction <= 32'h23bd0014;
+            20'd68:  instruction <= 32'h03e00008;
-            20'd69:  instruction <= 32'h03e00008;
+            20'd69:  instruction <= 32'h23bdffe0;
-            20'd70:  instruction <= 32'h23bdffe0;
+            20'd70:  instruction <= 32'hafbf0004;
-            20'd71:  instruction <= 32'hafbf0004;
+            20'd71:  instruction <= 32'hafb00008;
-            20'd72:  instruction <= 32'hafb00008;
+            20'd72:  instruction <= 32'hafb1000c;
-            20'd73:  instruction <= 32'hafb1000c;
+            20'd73:  instruction <= 32'hafb20010;
-            20'd74:  instruction <= 32'hafb20010;
+            20'd74:  instruction <= 32'hafb30014;
-            20'd75:  instruction <= 32'hafb30014;
+            20'd75:  instruction <= 32'hafb40018;
-            20'd76:  instruction <= 32'hafb40018;
+            20'd76:  instruction <= 32'hafb5001c;
-            20'd77:  instruction <= 32'hafb5001c;
+            20'd77:  instruction <= 32'hafb60020;
-            20'd78:  instruction <= 32'hafb60020;
+            20'd78:  instruction <= 32'h20900000;
-            20'd79:  instruction <= 32'h20900000;
+            20'd79:  instruction <= 32'h20b10000;
-            20'd80:  instruction <= 32'h20b10000;
+            20'd80:  instruction <= 32'h3c124000;
-            20'd81:  instruction <= 32'h3c124000;
+            20'd81:  instruction <= 32'h22520020;
-            20'd82:  instruction <= 32'h22520020;
+            20'd82:  instruction <= 32'h20130be2;
-            20'd83:  instruction <= 32'h20130be2;
+            20'd83:  instruction <= 32'h22140000;
-            20'd84:  instruction <= 32'h22140000;
+            20'd84:  instruction <= 32'h20160100;
-            20'd85:  instruction <= 32'h20160100;
+            20'd85:  instruction <= 32'h20150004;
-            20'd86:  instruction <= 32'h20150004;
+            20'd86:  instruction <= 32'h3288000f;
-            20'd87:  instruction <= 32'h3288000f;
+            20'd87:  instruction <= 32'h00084080;
-            20'd88:  instruction <= 32'h00084080;
+            20'd88:  instruction <= 32'h02484020;
-            20'd89:  instruction <= 32'h02484020;
+            20'd89:  instruction <= 32'h8d080000;
-            20'd90:  instruction <= 32'h8d080000;
+            20'd90:  instruction <= 32'h01164025;
-            20'd91:  instruction <= 32'h01164025;
+            20'd91:  instruction <= 32'hae280000;
-            20'd92:  instruction <= 32'hae280000;
+            20'd92:  instruction <= 32'h0014a102;
-            20'd93:  instruction <= 32'h0014a102;
+            20'd93:  instruction <= 32'h0016b040;
-            20'd94:  instruction <= 32'h0016b040;
+            20'd94:  instruction <= 32'h20080400;
-            20'd95:  instruction <= 32'h20080400;
+            20'd95:  instruction <= 32'h2108ffff;
-            20'd96:  instruction <= 32'h2108ffff;
+            20'd96:  instruction <= 32'h1d00fffe;
-            20'd97:  instruction <= 32'h1d00fffe;
+            20'd97:  instruction <= 32'h22b5ffff;
-            20'd98:  instruction <= 32'h22b5ffff;
+            20'd98:  instruction <= 32'h1ea0fff3;
-            20'd99:  instruction <= 32'h1ea0fff3;
+            20'd99:  instruction <= 32'h2273ffff;
-            20'd100: instruction <= 32'h2273ffff;
+            20'd100: instruction <= 32'h1e60ffee;
-            20'd101: instruction <= 32'h1e60ffee;
+            20'd101: instruction <= 32'h8fbf0004;
-            20'd102: instruction <= 32'h8fbf0004;
+            20'd102: instruction <= 32'h8fb00008;
-            20'd103: instruction <= 32'h8fb00008;
+            20'd103: instruction <= 32'h8fb1000c;
-            20'd104: instruction <= 32'h8fb1000c;
+            20'd104: instruction <= 32'h8fb20010;
-            20'd105: instruction <= 32'h8fb20010;
+            20'd105: instruction <= 32'h8fb30014;
-            20'd106: instruction <= 32'h8fb30014;
+            20'd106: instruction <= 32'h8fb40018;
-            20'd107: instruction <= 32'h8fb40018;
+            20'd107: instruction <= 32'h8fb5001c;
-            20'd108: instruction <= 32'h8fb5001c;
+            20'd108: instruction <= 32'h8fb60020;
-            20'd109: instruction <= 32'h8fb60020;
+            20'd109: instruction <= 32'h23bd0020;
-            20'd110: instruction <= 32'h23bd0020;
+            20'd110: instruction <= 32'h03e00008;
-            20'd111: instruction <= 32'h03e00008;
+            20'd111: instruction <= 32'h3c084000;
-            20'd112: instruction <= 32'h3c084000;
+            20'd112: instruction <= 32'h21080010;
-            20'd113: instruction <= 32'h21080010;
+            20'd113: instruction <= 32'had000000;
-            20'd114: instruction <= 32'had000000;
+            20'd114: instruction <= 32'h3c080100;
-            20'd115: instruction <= 32'h3c080100;
+            20'd115: instruction <= 32'h2108ffff;
-            20'd116: instruction <= 32'h2108ffff;
+            20'd116: instruction <= 32'h1d00fffe;
-            20'd117: instruction <= 32'h1d00fffe;
+            20'd117: instruction <= 32'h03e00008;
-            20'd118: instruction <= 32'h03e00008;
+            20'd118: instruction <= 32'h23bdfff4;
-            20'd119: instruction <= 32'h23bdfff4;
+            20'd119: instruction <= 32'hafbf0004;
-            20'd120: instruction <= 32'hafbf0004;
+            20'd120: instruction <= 32'hafb00008;
-            20'd121: instruction <= 32'hafb00008;
+            20'd121: instruction <= 32'hafb1000c;
-            20'd122: instruction <= 32'hafb1000c;
+            20'd122: instruction <= 32'h20900000;
-            20'd123: instruction <= 32'h20900000;
+            20'd123: instruction <= 32'h20110001;
-            20'd124: instruction <= 32'h20110001;
+            20'd124: instruction <= 32'h02114022;
-            20'd125: instruction <= 32'h02114022;
+            20'd125: instruction <= 32'h19000009;
-            20'd126: instruction <= 32'h19000009;
+            20'd126: instruction <= 32'h24040000;
-            20'd127: instruction <= 32'h24040000;
+            20'd127: instruction <= 32'h2225ffff;
-            20'd128: instruction <= 32'h2225ffff;
+            20'd128: instruction <= 32'h00113021;
-            20'd129: instruction <= 32'h00113021;
+            20'd129: instruction <= 32'h0c00008c;
-            20'd130: instruction <= 32'h0c00008d;
+            20'd130: instruction <= 32'h00022021;
-            20'd131: instruction <= 32'h00022021;
+            20'd131: instruction <= 32'h00112821;
-            20'd132: instruction <= 32'h00112821;
+            20'd132: instruction <= 32'h0c0000b1;
-            20'd133: instruction <= 32'h0c0000b2;
+            20'd133: instruction <= 32'h22310001;
-            20'd134: instruction <= 32'h22310001;
+            20'd134: instruction <= 32'h0800007c;
-            20'd135: instruction <= 32'h0800007d;
+            20'd135: instruction <= 32'h8fbf0004;
-            20'd136: instruction <= 32'h8fbf0004;
+            20'd136: instruction <= 32'h8fb00008;
-            20'd137: instruction <= 32'h8fb00008;
+            20'd137: instruction <= 32'h8fb1000c;
-            20'd138: instruction <= 32'h8fb1000c;
+            20'd138: instruction <= 32'h23bd000c;
-            20'd139: instruction <= 32'h23bd000c;
+            20'd139: instruction <= 32'h03e00008;
-            20'd140: instruction <= 32'h03e00008;
+            20'd140: instruction <= 32'h23bdffec;
-            20'd141: instruction <= 32'h23bdffec;
+            20'd141: instruction <= 32'hafb00004;
-            20'd142: instruction <= 32'hafb00004;
+            20'd142: instruction <= 32'hafb10008;
-            20'd143: instruction <= 32'hafb10008;
+            20'd143: instruction <= 32'hafb2000c;
-            20'd144: instruction <= 32'hafb2000c;
+            20'd144: instruction <= 32'hafb30010;
-            20'd145: instruction <= 32'hafb30010;
+            20'd145: instruction <= 32'hafbf0014;
-            20'd146: instruction <= 32'hafbf0014;
+            20'd146: instruction <= 32'h00854022;
-            20'd147: instruction <= 32'h00854022;
+            20'd147: instruction <= 32'h19000002;
-            20'd148: instruction <= 32'h19000002;
+            20'd148: instruction <= 32'h00801020;
-            20'd149: instruction <= 32'h00801020;
+            20'd149: instruction <= 32'h080000aa;
-            20'd150: instruction <= 32'h080000ab;
+            20'd150: instruction <= 32'h00048021;
-            20'd151: instruction <= 32'h00048021;
+            20'd151: instruction <= 32'h00058821;
-            20'd152: instruction <= 32'h00058821;
+            20'd152: instruction <= 32'h00069021;
-            20'd153: instruction <= 32'h00069021;
+            20'd153: instruction <= 32'h02119820;
-            20'd154: instruction <= 32'h02119820;
+            20'd154: instruction <= 32'h00139842;
-            20'd155: instruction <= 32'h00139842;
+            20'd155: instruction <= 32'h3c084000;
-            20'd156: instruction <= 32'h3c084000;
+            20'd156: instruction <= 32'h21080064;
-            20'd157: instruction <= 32'h21080064;
+            20'd157: instruction <= 32'h00134880;
-            20'd158: instruction <= 32'h00134880;
+            20'd158: instruction <= 32'h01284820;
-            20'd159: instruction <= 32'h01284820;
+            20'd159: instruction <= 32'h8d290000;
-            20'd160: instruction <= 32'h8d290000;
+            20'd160: instruction <= 32'h00125080;
-            20'd161: instruction <= 32'h00125080;
+            20'd161: instruction <= 32'h01485020;
-            20'd162: instruction <= 32'h01485020;
+            20'd162: instruction <= 32'h8d4a0000;
-            20'd163: instruction <= 32'h8d4a0000;
+            20'd163: instruction <= 32'h012a4022;
-            20'd164: instruction <= 32'h012a4022;
+            20'd164: instruction <= 32'h19000003;
-            20'd165: instruction <= 32'h19000003;
+            20'd165: instruction <= 32'h2265ffff;
-            20'd166: instruction <= 32'h2265ffff;
+            20'd166: instruction <= 32'h0c00008c;
-            20'd167: instruction <= 32'h0c00008d;
+            20'd167: instruction <= 32'h080000aa;
-            20'd168: instruction <= 32'h080000ab;
+            20'd168: instruction <= 32'h22640001;
-            20'd169: instruction <= 32'h22640001;
+            20'd169: instruction <= 32'h0c00008c;
-            20'd170: instruction <= 32'h0c00008d;
+            20'd170: instruction <= 32'h8fb00004;
-            20'd171: instruction <= 32'h8fb00004;
+            20'd171: instruction <= 32'h8fb10008;
-            20'd172: instruction <= 32'h8fb10008;
+            20'd172: instruction <= 32'h8fb2000c;
-            20'd173: instruction <= 32'h8fb2000c;
+            20'd173: instruction <= 32'h8fb30010;
-            20'd174: instruction <= 32'h8fb30010;
+            20'd174: instruction <= 32'h8fbf0014;
-            20'd175: instruction <= 32'h8fbf0014;
+            20'd175: instruction <= 32'h23bd0014;
-            20'd176: instruction <= 32'h23bd0014;
+            20'd176: instruction <= 32'h03e00008;
-            20'd177: instruction <= 32'h03e00008;
+            20'd177: instruction <= 32'h23bdfff4;
-            20'd178: instruction <= 32'h23bdfff4;
+            20'd178: instruction <= 32'hafb00004;
-            20'd179: instruction <= 32'hafb00004;
+            20'd179: instruction <= 32'hafb10008;
-            20'd180: instruction <= 32'hafb10008;
+            20'd180: instruction <= 32'hafbf000c;
-            20'd181: instruction <= 32'hafbf000c;
+            20'd181: instruction <= 32'h3c104000;
-            20'd182: instruction <= 32'h3c104000;
+            20'd182: instruction <= 32'h22100064;
-            20'd183: instruction <= 32'h22100064;
+            20'd183: instruction <= 32'h00054080;
-            20'd184: instruction <= 32'h00054080;
+            20'd184: instruction <= 32'h02089020;
-            20'd185: instruction <= 32'h02089020;
+            20'd185: instruction <= 32'h8e520000;
-            20'd186: instruction <= 32'h8e520000;
+            20'd186: instruction <= 32'h20b1ffff;
-            20'd187: instruction <= 32'h20b1ffff;
+            20'd187: instruction <= 32'h02244022;
-            20'd188: instruction <= 32'h02244022;
+            20'd188: instruction <= 32'h05000006;
-            20'd189: instruction <= 32'h05000006;
+            20'd189: instruction <= 32'h00114080;
-            20'd190: instruction <= 32'h00114080;
+            20'd190: instruction <= 32'h02084020;
-            20'd191: instruction <= 32'h02084020;
+            20'd191: instruction <= 32'h8d090000;
-            20'd192: instruction <= 32'h8d090000;
+            20'd192: instruction <= 32'had090004;
-            20'd193: instruction <= 32'had090004;
+            20'd193: instruction <= 32'h2231ffff;
-            20'd194: instruction <= 32'h2231ffff;
+            20'd194: instruction <= 32'h080000bb;
-            20'd195: instruction <= 32'h080000bc;
+            20'd195: instruction <= 32'h00044080;
-            20'd196: instruction <= 32'h00044080;
+            20'd196: instruction <= 32'h02084020;
-            20'd197: instruction <= 32'h02084020;
+            20'd197: instruction <= 32'had120000;
-            20'd198: instruction <= 32'had120000;
+            20'd198: instruction <= 32'h8fb00004;
-            20'd199: instruction <= 32'h8fb00004;
+            20'd199: instruction <= 32'h8fb10008;
-            20'd200: instruction <= 32'h8fb10008;
+            20'd200: instruction <= 32'h8fbf000c;
-            20'd201: instruction <= 32'h8fbf000c;
+            20'd201: instruction <= 32'h23bd000c;
-            20'd202: instruction <= 32'h23bd000c;
+            20'd202: instruction <= 32'h03e00008;
            20'd203: instruction <= 32'h03e00008;
            default: instruction <= 32'h00000000;
        endcase
    end
--- a/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
+++ b/PipelineProcessor.srcs/utils_1/imports/synth_1/CPU.dcp
--- a/PipelineProcessor.xpr
+++ b/PipelineProcessor.xpr
@@ -60,7 +60,7 @@
    <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
    <Option Name="EnableBDX" Val="FALSE"/>
    <Option Name="FeatureSet" Val="FeatureSet_Classic"/>
-    <Option Name="WTXSimLaunchSim" Val="319"/>
+    <Option Name="WTXSimLaunchSim" Val="337"/>
    <Option Name="WTModelSimLaunchSim" Val="0"/>
    <Option Name="WTQuestaLaunchSim" Val="0"/>
    <Option Name="WTIesLaunchSim" Val="0"/>