Initial commit
This commit is contained in:
86
.gitignore
vendored
Normal file
86
.gitignore
vendored
Normal file
@@ -0,0 +1,86 @@
|
|||||||
|
#########################################################################################################
|
||||||
|
## This is an example .gitignore file for Vivado, please treat it as an example as
|
||||||
|
## it might not be complete. In addition, XAPP 1165 should be followed.
|
||||||
|
#########################################################################################################
|
||||||
|
#########
|
||||||
|
#Exclude all
|
||||||
|
#########
|
||||||
|
*
|
||||||
|
!*/
|
||||||
|
!.gitignore
|
||||||
|
###########################################################################
|
||||||
|
## VIVADO
|
||||||
|
###########################################################################
|
||||||
|
#########
|
||||||
|
#Source files:
|
||||||
|
#########
|
||||||
|
#Do NOT ignore VHDL, Verilog, block diagrams or EDIF files.
|
||||||
|
!*.vhd
|
||||||
|
!*.v
|
||||||
|
!*.bd
|
||||||
|
!*.edif
|
||||||
|
#########
|
||||||
|
#IP files
|
||||||
|
#########
|
||||||
|
#.xci: synthesis and implemented not possible - you need to return back to the previous version to generate output products
|
||||||
|
#.xci + .dcp: implementation possible but not re-synthesis
|
||||||
|
#*.xci(www.spiritconsortium.org)
|
||||||
|
!*.xci
|
||||||
|
#*.dcp(checkpoint files)
|
||||||
|
!*.dcp
|
||||||
|
!*.vds
|
||||||
|
!*.pb
|
||||||
|
#All bd comments and layout coordinates are stored within .ui
|
||||||
|
!*.ui
|
||||||
|
!*.ooc
|
||||||
|
#########
|
||||||
|
#System Generator
|
||||||
|
#########
|
||||||
|
!*.mdl
|
||||||
|
!*.slx
|
||||||
|
!*.bxml
|
||||||
|
#########
|
||||||
|
#Simulation logic analyzer
|
||||||
|
#########
|
||||||
|
!*.wcfg
|
||||||
|
!*.coe
|
||||||
|
#########
|
||||||
|
#MIG
|
||||||
|
#########
|
||||||
|
!*.prj
|
||||||
|
!*.mem
|
||||||
|
#########
|
||||||
|
#Project files
|
||||||
|
#########
|
||||||
|
#XPR + *.XML ? XPR (Files are merged into a single XPR file for 2014.1 version)
|
||||||
|
#Do NOT ignore *.xpr files
|
||||||
|
!*.xpr
|
||||||
|
#Include *.xml files for 2013.4 or earlier version
|
||||||
|
#!*.xml
|
||||||
|
#########
|
||||||
|
#Constraint files
|
||||||
|
#########
|
||||||
|
#Do NOT ignore *.xdc files
|
||||||
|
!*.xdc
|
||||||
|
#########
|
||||||
|
#TCL - files
|
||||||
|
#########
|
||||||
|
!*.tcl
|
||||||
|
#########
|
||||||
|
#Journal - files
|
||||||
|
#########
|
||||||
|
!*.jou
|
||||||
|
#########
|
||||||
|
#Reports
|
||||||
|
#########
|
||||||
|
!*.rpt
|
||||||
|
!*.txt
|
||||||
|
!*.vdi
|
||||||
|
#########
|
||||||
|
#C-files
|
||||||
|
#########
|
||||||
|
!*.c
|
||||||
|
!*.h
|
||||||
|
!*.elf
|
||||||
|
!*.bmm
|
||||||
|
!*.xmp
|
||||||
@@ -0,0 +1,295 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||||
|
<spirit:vendor>xilinx.com</spirit:vendor>
|
||||||
|
<spirit:library>ipcache</spirit:library>
|
||||||
|
<spirit:name>a4c5028597ba9ab4</spirit:name>
|
||||||
|
<spirit:version>0</spirit:version>
|
||||||
|
<spirit:componentInstances>
|
||||||
|
<spirit:componentInstance>
|
||||||
|
<spirit:instanceName>phase_locked_loop</spirit:instanceName>
|
||||||
|
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
|
||||||
|
<spirit:configurableElementValues>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">446.763</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">313.282</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">10.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">phase_locked_loop</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">41</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">82</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">5</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a35t</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fgg484</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">e6a05ff8</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">a4c5028597ba9ab4</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">phase_locked_loop</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 4016217 $</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">401ad827</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">34</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">13</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2023.2</spirit:configurableElementValue>
|
||||||
|
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
|
||||||
|
</spirit:configurableElementValues>
|
||||||
|
</spirit:componentInstance>
|
||||||
|
</spirit:componentInstances>
|
||||||
|
</spirit:design>
|
||||||
Binary file not shown.
@@ -0,0 +1,220 @@
|
|||||||
|
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||||
|
// Date : Tue Jul 9 23:44:24 2024
|
||||||
|
// Host : Viviana running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||||
|
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.v
|
||||||
|
// Design : phase_locked_loop
|
||||||
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
// Device : xc7a35tfgg484-1
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
(* NotValidForBitStream *)
|
||||||
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
|
||||||
|
(clk_out1,
|
||||||
|
reset,
|
||||||
|
locked,
|
||||||
|
clk_in1);
|
||||||
|
output clk_out1;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
|
||||||
|
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||||
|
wire clk_out1;
|
||||||
|
wire locked;
|
||||||
|
wire reset;
|
||||||
|
|
||||||
|
decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_phase_locked_loop_clk_wiz inst
|
||||||
|
(.clk_in1(clk_in1),
|
||||||
|
.clk_out1(clk_out1),
|
||||||
|
.locked(locked),
|
||||||
|
.reset(reset));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_phase_locked_loop_clk_wiz
|
||||||
|
(clk_out1,
|
||||||
|
reset,
|
||||||
|
locked,
|
||||||
|
clk_in1);
|
||||||
|
output clk_out1;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
|
||||||
|
wire clk_in1;
|
||||||
|
wire clk_in1_phase_locked_loop;
|
||||||
|
wire clk_out1;
|
||||||
|
wire clk_out1_phase_locked_loop;
|
||||||
|
wire clkfbout_buf_phase_locked_loop;
|
||||||
|
wire clkfbout_phase_locked_loop;
|
||||||
|
wire locked;
|
||||||
|
wire reset;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
|
||||||
|
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
|
||||||
|
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
BUFG clkf_buf
|
||||||
|
(.I(clkfbout_phase_locked_loop),
|
||||||
|
.O(clkfbout_buf_phase_locked_loop));
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
(* CAPACITANCE = "DONT_CARE" *)
|
||||||
|
(* IBUF_DELAY_VALUE = "0" *)
|
||||||
|
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||||
|
IBUF #(
|
||||||
|
.IOSTANDARD("DEFAULT"))
|
||||||
|
clkin1_ibufg
|
||||||
|
(.I(clk_in1),
|
||||||
|
.O(clk_in1_phase_locked_loop));
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
BUFG clkout1_buf
|
||||||
|
(.I(clk_out1_phase_locked_loop),
|
||||||
|
.O(clk_out1));
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
PLLE2_ADV #(
|
||||||
|
.BANDWIDTH("OPTIMIZED"),
|
||||||
|
.CLKFBOUT_MULT(41),
|
||||||
|
.CLKFBOUT_PHASE(0.000000),
|
||||||
|
.CLKIN1_PERIOD(10.000000),
|
||||||
|
.CLKIN2_PERIOD(0.000000),
|
||||||
|
.CLKOUT0_DIVIDE(82),
|
||||||
|
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT0_PHASE(0.000000),
|
||||||
|
.CLKOUT1_DIVIDE(1),
|
||||||
|
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT1_PHASE(0.000000),
|
||||||
|
.CLKOUT2_DIVIDE(1),
|
||||||
|
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT2_PHASE(0.000000),
|
||||||
|
.CLKOUT3_DIVIDE(1),
|
||||||
|
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT3_PHASE(0.000000),
|
||||||
|
.CLKOUT4_DIVIDE(1),
|
||||||
|
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT4_PHASE(0.000000),
|
||||||
|
.CLKOUT5_DIVIDE(1),
|
||||||
|
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT5_PHASE(0.000000),
|
||||||
|
.COMPENSATION("ZHOLD"),
|
||||||
|
.DIVCLK_DIVIDE(5),
|
||||||
|
.IS_CLKINSEL_INVERTED(1'b0),
|
||||||
|
.IS_PWRDWN_INVERTED(1'b0),
|
||||||
|
.IS_RST_INVERTED(1'b0),
|
||||||
|
.REF_JITTER1(0.010000),
|
||||||
|
.REF_JITTER2(0.010000),
|
||||||
|
.STARTUP_WAIT("FALSE"))
|
||||||
|
plle2_adv_inst
|
||||||
|
(.CLKFBIN(clkfbout_buf_phase_locked_loop),
|
||||||
|
.CLKFBOUT(clkfbout_phase_locked_loop),
|
||||||
|
.CLKIN1(clk_in1_phase_locked_loop),
|
||||||
|
.CLKIN2(1'b0),
|
||||||
|
.CLKINSEL(1'b1),
|
||||||
|
.CLKOUT0(clk_out1_phase_locked_loop),
|
||||||
|
.CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
|
||||||
|
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
|
||||||
|
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
|
||||||
|
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
|
||||||
|
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
|
||||||
|
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.DCLK(1'b0),
|
||||||
|
.DEN(1'b0),
|
||||||
|
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
|
||||||
|
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
|
||||||
|
.DWE(1'b0),
|
||||||
|
.LOCKED(locked),
|
||||||
|
.PWRDWN(1'b0),
|
||||||
|
.RST(reset));
|
||||||
|
endmodule
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
parameter GRES_WIDTH = 10000;
|
||||||
|
parameter GRES_START = 10000;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
wire GRESTORE;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
reg GRESTORE_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
#(GRES_START);
|
||||||
|
GRESTORE_int = 1'b1;
|
||||||
|
#(GRES_WIDTH);
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
@@ -0,0 +1,24 @@
|
|||||||
|
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||||
|
// Date : Tue Jul 9 23:44:24 2024
|
||||||
|
// Host : Viviana running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
|
||||||
|
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.v
|
||||||
|
// Design : phase_locked_loop
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7a35tfgg484-1
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, reset, locked, clk_in1)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
|
||||||
|
/* synthesis syn_force_seq_prim="clk_out1" */;
|
||||||
|
output clk_out1 /* synthesis syn_isclock = 1 */;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,311 @@
|
|||||||
|
2023.2:
|
||||||
|
* Version 6.0 (Rev. 13)
|
||||||
|
* Bug Fix: CR Fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2023.1.2:
|
||||||
|
* Version 6.0 (Rev. 12)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2023.1.1:
|
||||||
|
* Version 6.0 (Rev. 12)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2023.1:
|
||||||
|
* Version 6.0 (Rev. 12)
|
||||||
|
* Bug Fix: CR Fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2022.2.2:
|
||||||
|
* Version 6.0 (Rev. 11)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2022.2.1:
|
||||||
|
* Version 6.0 (Rev. 11)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2022.2:
|
||||||
|
* Version 6.0 (Rev. 11)
|
||||||
|
* Bug Fix: CR Fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2022.1.2:
|
||||||
|
* Version 6.0 (Rev. 10)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2022.1.1:
|
||||||
|
* Version 6.0 (Rev. 10)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2022.1:
|
||||||
|
* Version 6.0 (Rev. 10)
|
||||||
|
* Bug Fix: CR Fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2021.2.2:
|
||||||
|
* Version 6.0 (Rev. 9)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2021.2.1:
|
||||||
|
* Version 6.0 (Rev. 9)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2021.2:
|
||||||
|
* Version 6.0 (Rev. 9)
|
||||||
|
* Bug Fix: CR Fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2021.1.1:
|
||||||
|
* Version 6.0 (Rev. 8)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2021.1:
|
||||||
|
* Version 6.0 (Rev. 8)
|
||||||
|
* Bug Fix: Internal GUI fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2020.3:
|
||||||
|
* Version 6.0 (Rev. 7)
|
||||||
|
* Bug Fix: Internal GUI fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2020.2.2:
|
||||||
|
* Version 6.0 (Rev. 6)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2020.2.1:
|
||||||
|
* Version 6.0 (Rev. 6)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2020.2:
|
||||||
|
* Version 6.0 (Rev. 6)
|
||||||
|
* Bug Fix: Internal GUI fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2020.1.1:
|
||||||
|
* Version 6.0 (Rev. 5)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2020.1:
|
||||||
|
* Version 6.0 (Rev. 5)
|
||||||
|
* Bug Fix: Internal GUI fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2019.2.2:
|
||||||
|
* Version 6.0 (Rev. 4)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2019.2.1:
|
||||||
|
* Version 6.0 (Rev. 4)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2019.2:
|
||||||
|
* Version 6.0 (Rev. 4)
|
||||||
|
* Bug Fix: Internal GUI fixes
|
||||||
|
* Other: CR Fixes
|
||||||
|
|
||||||
|
2019.1.3:
|
||||||
|
* Version 6.0 (Rev. 3)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2019.1.2:
|
||||||
|
* Version 6.0 (Rev. 3)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2019.1.1:
|
||||||
|
* Version 6.0 (Rev. 3)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2019.1:
|
||||||
|
* Version 6.0 (Rev. 3)
|
||||||
|
* Bug Fix: Internal GUI fixes
|
||||||
|
* Other: New family support added
|
||||||
|
|
||||||
|
2018.3.1:
|
||||||
|
* Version 6.0 (Rev. 2)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2018.3:
|
||||||
|
* Version 6.0 (Rev. 2)
|
||||||
|
* Bug Fix: Made input source independent for primary and secondary clock
|
||||||
|
* Other: New family support added
|
||||||
|
|
||||||
|
2018.2:
|
||||||
|
* Version 6.0 (Rev. 1)
|
||||||
|
* Bug Fix: Removed vco freq check when Primitive is None
|
||||||
|
* Other: New family support added
|
||||||
|
|
||||||
|
2018.1:
|
||||||
|
* Version 6.0
|
||||||
|
* Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature
|
||||||
|
* Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI
|
||||||
|
* Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals.
|
||||||
|
* Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support
|
||||||
|
* Other: DRCs added for invalid input values in Override mode
|
||||||
|
|
||||||
|
2017.4:
|
||||||
|
* Version 5.4 (Rev. 3)
|
||||||
|
* Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL
|
||||||
|
* Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4
|
||||||
|
|
||||||
|
2017.3:
|
||||||
|
* Version 5.4 (Rev. 2)
|
||||||
|
* General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices
|
||||||
|
|
||||||
|
2017.2:
|
||||||
|
* Version 5.4 (Rev. 1)
|
||||||
|
* General: Internal GUI changes. No effect on the customer design.
|
||||||
|
|
||||||
|
2017.1:
|
||||||
|
* Version 5.4
|
||||||
|
* Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices.
|
||||||
|
* Other: Added support for new zynq ultrascale plus devices.
|
||||||
|
|
||||||
|
2016.4:
|
||||||
|
* Version 5.3 (Rev. 3)
|
||||||
|
* Bug Fix: Internal GUI issues are fixed.
|
||||||
|
|
||||||
|
2016.3:
|
||||||
|
* Version 5.3 (Rev. 2)
|
||||||
|
* Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.
|
||||||
|
* Feature Enhancement: Added Matched Routing Option for better timing solutions.
|
||||||
|
* Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.
|
||||||
|
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
|
||||||
|
* Other: Added support for Spartan7 devices.
|
||||||
|
|
||||||
|
2016.2:
|
||||||
|
* Version 5.3 (Rev. 1)
|
||||||
|
* Internal register bit update, no effect on customer designs.
|
||||||
|
|
||||||
|
2016.1:
|
||||||
|
* Version 5.3
|
||||||
|
* Added Clock Monitor Feature as part of clocking wizard
|
||||||
|
* DRP registers can be directly written through AXI without resource utilization
|
||||||
|
* Changes to HDL library management to support Vivado IP simulation library
|
||||||
|
|
||||||
|
2015.4.2:
|
||||||
|
* Version 5.2 (Rev. 1)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2015.4.1:
|
||||||
|
* Version 5.2 (Rev. 1)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2015.4:
|
||||||
|
* Version 5.2 (Rev. 1)
|
||||||
|
* Internal device family change, no functional changes
|
||||||
|
|
||||||
|
2015.3:
|
||||||
|
* Version 5.2
|
||||||
|
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
|
||||||
|
* Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
|
||||||
|
* Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
|
||||||
|
* When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
|
||||||
|
* Example design and simulation files are delivered in verilog only
|
||||||
|
|
||||||
|
2015.2.1:
|
||||||
|
* Version 5.1 (Rev. 6)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2015.2:
|
||||||
|
* Version 5.1 (Rev. 6)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2015.1:
|
||||||
|
* Version 5.1 (Rev. 6)
|
||||||
|
* Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
|
||||||
|
* Supported devices and production status are now determined automatically, to simplify support for future devices
|
||||||
|
|
||||||
|
2014.4.1:
|
||||||
|
* Version 5.1 (Rev. 5)
|
||||||
|
* No changes
|
||||||
|
|
||||||
|
2014.4:
|
||||||
|
* Version 5.1 (Rev. 5)
|
||||||
|
* Internal device family change, no functional changes
|
||||||
|
* updates related to the source selection based on board interface for zed board
|
||||||
|
|
||||||
|
2014.3:
|
||||||
|
* Version 5.1 (Rev. 4)
|
||||||
|
* Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
|
||||||
|
|
||||||
|
2014.2:
|
||||||
|
* Version 5.1 (Rev. 3)
|
||||||
|
* Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
|
||||||
|
|
||||||
|
2014.1:
|
||||||
|
* Version 5.1 (Rev. 2)
|
||||||
|
* Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
|
||||||
|
* Internal device family name change, no functional changes
|
||||||
|
|
||||||
|
2013.4:
|
||||||
|
* Version 5.1 (Rev. 1)
|
||||||
|
* Added support for Ultrascale devices
|
||||||
|
* Updated Board Flow GUI to select the clock interfaces
|
||||||
|
* Fixed issue with Stub file parameter error for BUFR output driver
|
||||||
|
|
||||||
|
2013.3:
|
||||||
|
* Version 5.1
|
||||||
|
* Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
|
||||||
|
* Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
|
||||||
|
* Fixed precision issues between displayed and actual frequencies
|
||||||
|
* Added tool tips to GUI
|
||||||
|
* Added Jitter and Phase error values to IP properties
|
||||||
|
* Added support for Cadence IES and Synopsys VCS simulators
|
||||||
|
* Reduced warnings in synthesis and simulation
|
||||||
|
* Enhanced support for IP Integrator
|
||||||
|
|
||||||
|
2013.2:
|
||||||
|
* Version 5.0 (Rev. 1)
|
||||||
|
* Fixed issue with clock constraints for multiple instances of clocking wizard
|
||||||
|
* Updated Life-Cycle status of devices
|
||||||
|
|
||||||
|
2013.1:
|
||||||
|
* Version 5.0
|
||||||
|
* Lower case ports for Verilog
|
||||||
|
* Added Safe Clock Startup and Clock Sequencing
|
||||||
|
|
||||||
|
(c) Copyright 2008 - 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||||
|
|
||||||
|
This file contains confidential and proprietary information
|
||||||
|
of AMD and is protected under U.S. and international copyright
|
||||||
|
and other intellectual property laws.
|
||||||
|
|
||||||
|
DISCLAIMER
|
||||||
|
This disclaimer is not a license and does not grant any
|
||||||
|
rights to the materials distributed herewith. Except as
|
||||||
|
otherwise provided in a valid license issued to you by
|
||||||
|
AMD, and to the maximum extent permitted by applicable
|
||||||
|
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
(2) AMD shall not be liable (whether in contract or tort,
|
||||||
|
including negligence, or under any other theory of
|
||||||
|
liability) for any loss or damage of any kind or nature
|
||||||
|
related to, arising under or in connection with these
|
||||||
|
materials, including for any direct, or any indirect,
|
||||||
|
special, incidental, or consequential loss or damage
|
||||||
|
(including loss of data, profits, goodwill, or any type of
|
||||||
|
loss or damage suffered as a result of any action brought
|
||||||
|
by a third party) even if such damage or loss was
|
||||||
|
reasonably foreseeable or AMD had been advised of the
|
||||||
|
possibility of the same.
|
||||||
|
|
||||||
|
CRITICAL APPLICATIONS
|
||||||
|
AMD products are not designed or intended to be fail-
|
||||||
|
safe, or for use in any application requiring fail-safe
|
||||||
|
performance, such as life-support or safety devices or
|
||||||
|
systems, Class III medical devices, nuclear facilities,
|
||||||
|
applications related to the deployment of airbags, or any
|
||||||
|
other applications that could lead to death, personal
|
||||||
|
injury, or severe property or environmental damage
|
||||||
|
(individually and collectively, "Critical
|
||||||
|
Applications"). Customer assumes the sole risk and
|
||||||
|
liability of any use of AMD products in Critical
|
||||||
|
Applications, subject only to applicable laws and
|
||||||
|
regulations governing limitations on product liability.
|
||||||
|
|
||||||
|
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
PART OF THIS FILE AT ALL TIMES.
|
||||||
Binary file not shown.
@@ -0,0 +1,89 @@
|
|||||||
|
|
||||||
|
// file: phase_locked_loop.v
|
||||||
|
// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of AMD and is protected under U.S. and international copyright
|
||||||
|
// and other intellectual property laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// AMD, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) AMD shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or AMD had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// AMD products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of AMD products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// User entered comments
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// None
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||||
|
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// clk_out1__10.00000______0.000______50.0______446.763____313.282
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// __primary_________100.000____________0.010
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
(* CORE_GENERATION_INFO = "phase_locked_loop,clk_wiz_v6_0_13_0_0,{component_name=phase_locked_loop,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
|
||||||
|
|
||||||
|
module phase_locked_loop
|
||||||
|
(
|
||||||
|
// Clock out ports
|
||||||
|
output clk_out1,
|
||||||
|
// Status and control signals
|
||||||
|
input reset,
|
||||||
|
output locked,
|
||||||
|
// Clock in ports
|
||||||
|
input clk_in1
|
||||||
|
);
|
||||||
|
|
||||||
|
phase_locked_loop_clk_wiz inst
|
||||||
|
(
|
||||||
|
// Clock out ports
|
||||||
|
.clk_out1(clk_out1),
|
||||||
|
// Status and control signals
|
||||||
|
.reset(reset),
|
||||||
|
.locked(locked),
|
||||||
|
// Clock in ports
|
||||||
|
.clk_in1(clk_in1)
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,57 @@
|
|||||||
|
|
||||||
|
# file: phase_locked_loop.xdc
|
||||||
|
# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of AMD and is protected under U.S. and international copyright
|
||||||
|
# and other intellectual property laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# AMD, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) AMD shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or AMD had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# AMD products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of AMD products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
|
||||||
|
# Input clock periods. These duplicate the values entered for the
|
||||||
|
# input clocks. You can use these to time your system. If required
|
||||||
|
# commented constraints can be used in the top level xdc
|
||||||
|
#----------------------------------------------------------------
|
||||||
|
# Connect to input port when clock capable pin is selected for input
|
||||||
|
create_clock -period 10.000 [get_ports clk_in1]
|
||||||
|
set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100
|
||||||
|
|
||||||
|
|
||||||
|
set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]
|
||||||
@@ -0,0 +1,2 @@
|
|||||||
|
#--------------------Physical Constraints-----------------
|
||||||
|
|
||||||
@@ -0,0 +1,181 @@
|
|||||||
|
|
||||||
|
// file: phase_locked_loop.v
|
||||||
|
// (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||||
|
//
|
||||||
|
// This file contains confidential and proprietary information
|
||||||
|
// of AMD and is protected under U.S. and international copyright
|
||||||
|
// and other intellectual property laws.
|
||||||
|
//
|
||||||
|
// DISCLAIMER
|
||||||
|
// This disclaimer is not a license and does not grant any
|
||||||
|
// rights to the materials distributed herewith. Except as
|
||||||
|
// otherwise provided in a valid license issued to you by
|
||||||
|
// AMD, and to the maximum extent permitted by applicable
|
||||||
|
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
// WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
// (2) AMD shall not be liable (whether in contract or tort,
|
||||||
|
// including negligence, or under any other theory of
|
||||||
|
// liability) for any loss or damage of any kind or nature
|
||||||
|
// related to, arising under or in connection with these
|
||||||
|
// materials, including for any direct, or any indirect,
|
||||||
|
// special, incidental, or consequential loss or damage
|
||||||
|
// (including loss of data, profits, goodwill, or any type of
|
||||||
|
// loss or damage suffered as a result of any action brought
|
||||||
|
// by a third party) even if such damage or loss was
|
||||||
|
// reasonably foreseeable or AMD had been advised of the
|
||||||
|
// possibility of the same.
|
||||||
|
//
|
||||||
|
// CRITICAL APPLICATIONS
|
||||||
|
// AMD products are not designed or intended to be fail-
|
||||||
|
// safe, or for use in any application requiring fail-safe
|
||||||
|
// performance, such as life-support or safety devices or
|
||||||
|
// systems, Class III medical devices, nuclear facilities,
|
||||||
|
// applications related to the deployment of airbags, or any
|
||||||
|
// other applications that could lead to death, personal
|
||||||
|
// injury, or severe property or environmental damage
|
||||||
|
// (individually and collectively, "Critical
|
||||||
|
// Applications"). Customer assumes the sole risk and
|
||||||
|
// liability of any use of AMD products in Critical
|
||||||
|
// Applications, subject only to applicable laws and
|
||||||
|
// regulations governing limitations on product liability.
|
||||||
|
//
|
||||||
|
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
// PART OF THIS FILE AT ALL TIMES.
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// User entered comments
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// None
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Output Output Phase Duty Cycle Pk-to-Pk Phase
|
||||||
|
// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// clk_out1__10.00000______0.000______50.0______446.763____313.282
|
||||||
|
//
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// Input Clock Freq (MHz) Input Jitter (UI)
|
||||||
|
//----------------------------------------------------------------------------
|
||||||
|
// __primary_________100.000____________0.010
|
||||||
|
|
||||||
|
`timescale 1ps/1ps
|
||||||
|
|
||||||
|
module phase_locked_loop_clk_wiz
|
||||||
|
|
||||||
|
(// Clock in ports
|
||||||
|
// Clock out ports
|
||||||
|
output clk_out1,
|
||||||
|
// Status and control signals
|
||||||
|
input reset,
|
||||||
|
output locked,
|
||||||
|
input clk_in1
|
||||||
|
);
|
||||||
|
// Input buffering
|
||||||
|
//------------------------------------
|
||||||
|
wire clk_in1_phase_locked_loop;
|
||||||
|
wire clk_in2_phase_locked_loop;
|
||||||
|
IBUF clkin1_ibufg
|
||||||
|
(.O (clk_in1_phase_locked_loop),
|
||||||
|
.I (clk_in1));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
// Clocking PRIMITIVE
|
||||||
|
//------------------------------------
|
||||||
|
|
||||||
|
// Instantiation of the MMCM PRIMITIVE
|
||||||
|
// * Unused inputs are tied off
|
||||||
|
// * Unused outputs are labeled unused
|
||||||
|
|
||||||
|
wire clk_out1_phase_locked_loop;
|
||||||
|
wire clk_out2_phase_locked_loop;
|
||||||
|
wire clk_out3_phase_locked_loop;
|
||||||
|
wire clk_out4_phase_locked_loop;
|
||||||
|
wire clk_out5_phase_locked_loop;
|
||||||
|
wire clk_out6_phase_locked_loop;
|
||||||
|
wire clk_out7_phase_locked_loop;
|
||||||
|
|
||||||
|
wire [15:0] do_unused;
|
||||||
|
wire drdy_unused;
|
||||||
|
wire psdone_unused;
|
||||||
|
wire locked_int;
|
||||||
|
wire clkfbout_phase_locked_loop;
|
||||||
|
wire clkfbout_buf_phase_locked_loop;
|
||||||
|
wire clkfboutb_unused;
|
||||||
|
wire clkout1_unused;
|
||||||
|
wire clkout2_unused;
|
||||||
|
wire clkout3_unused;
|
||||||
|
wire clkout4_unused;
|
||||||
|
wire clkout5_unused;
|
||||||
|
wire clkout6_unused;
|
||||||
|
wire clkfbstopped_unused;
|
||||||
|
wire clkinstopped_unused;
|
||||||
|
wire reset_high;
|
||||||
|
|
||||||
|
PLLE2_ADV
|
||||||
|
#(.BANDWIDTH ("OPTIMIZED"),
|
||||||
|
.COMPENSATION ("ZHOLD"),
|
||||||
|
.STARTUP_WAIT ("FALSE"),
|
||||||
|
.DIVCLK_DIVIDE (5),
|
||||||
|
.CLKFBOUT_MULT (41),
|
||||||
|
.CLKFBOUT_PHASE (0.000),
|
||||||
|
.CLKOUT0_DIVIDE (82),
|
||||||
|
.CLKOUT0_PHASE (0.000),
|
||||||
|
.CLKOUT0_DUTY_CYCLE (0.500),
|
||||||
|
.CLKIN1_PERIOD (10.000))
|
||||||
|
plle2_adv_inst
|
||||||
|
// Output clocks
|
||||||
|
(
|
||||||
|
.CLKFBOUT (clkfbout_phase_locked_loop),
|
||||||
|
.CLKOUT0 (clk_out1_phase_locked_loop),
|
||||||
|
.CLKOUT1 (clkout1_unused),
|
||||||
|
.CLKOUT2 (clkout2_unused),
|
||||||
|
.CLKOUT3 (clkout3_unused),
|
||||||
|
.CLKOUT4 (clkout4_unused),
|
||||||
|
.CLKOUT5 (clkout5_unused),
|
||||||
|
// Input clock control
|
||||||
|
.CLKFBIN (clkfbout_buf_phase_locked_loop),
|
||||||
|
.CLKIN1 (clk_in1_phase_locked_loop),
|
||||||
|
.CLKIN2 (1'b0),
|
||||||
|
// Tied to always select the primary input clock
|
||||||
|
.CLKINSEL (1'b1),
|
||||||
|
// Ports for dynamic reconfiguration
|
||||||
|
.DADDR (7'h0),
|
||||||
|
.DCLK (1'b0),
|
||||||
|
.DEN (1'b0),
|
||||||
|
.DI (16'h0),
|
||||||
|
.DO (do_unused),
|
||||||
|
.DRDY (drdy_unused),
|
||||||
|
.DWE (1'b0),
|
||||||
|
// Other control and status signals
|
||||||
|
.LOCKED (locked_int),
|
||||||
|
.PWRDWN (1'b0),
|
||||||
|
.RST (reset_high));
|
||||||
|
assign reset_high = reset;
|
||||||
|
|
||||||
|
assign locked = locked_int;
|
||||||
|
// Clock Monitor clock assigning
|
||||||
|
//--------------------------------------
|
||||||
|
// Output buffering
|
||||||
|
//-----------------------------------
|
||||||
|
|
||||||
|
BUFG clkf_buf
|
||||||
|
(.O (clkfbout_buf_phase_locked_loop),
|
||||||
|
.I (clkfbout_phase_locked_loop));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
BUFG clkout1_buf
|
||||||
|
(.O (clk_out1),
|
||||||
|
.I (clk_out1_phase_locked_loop));
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,55 @@
|
|||||||
|
|
||||||
|
# file: phase_locked_loop_ooc.xdc
|
||||||
|
# (c) Copyright 2017-2018, 2023 Advanced Micro Devices, Inc. All rights reserved.
|
||||||
|
#
|
||||||
|
# This file contains confidential and proprietary information
|
||||||
|
# of AMD and is protected under U.S. and international copyright
|
||||||
|
# and other intellectual property laws.
|
||||||
|
#
|
||||||
|
# DISCLAIMER
|
||||||
|
# This disclaimer is not a license and does not grant any
|
||||||
|
# rights to the materials distributed herewith. Except as
|
||||||
|
# otherwise provided in a valid license issued to you by
|
||||||
|
# AMD, and to the maximum extent permitted by applicable
|
||||||
|
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||||
|
# WITH ALL FAULTS, AND AMD HEREBY DISCLAIMS ALL WARRANTIES
|
||||||
|
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||||
|
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||||
|
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||||
|
# (2) AMD shall not be liable (whether in contract or tort,
|
||||||
|
# including negligence, or under any other theory of
|
||||||
|
# liability) for any loss or damage of any kind or nature
|
||||||
|
# related to, arising under or in connection with these
|
||||||
|
# materials, including for any direct, or any indirect,
|
||||||
|
# special, incidental, or consequential loss or damage
|
||||||
|
# (including loss of data, profits, goodwill, or any type of
|
||||||
|
# loss or damage suffered as a result of any action brought
|
||||||
|
# by a third party) even if such damage or loss was
|
||||||
|
# reasonably foreseeable or AMD had been advised of the
|
||||||
|
# possibility of the same.
|
||||||
|
#
|
||||||
|
# CRITICAL APPLICATIONS
|
||||||
|
# AMD products are not designed or intended to be fail-
|
||||||
|
# safe, or for use in any application requiring fail-safe
|
||||||
|
# performance, such as life-support or safety devices or
|
||||||
|
# systems, Class III medical devices, nuclear facilities,
|
||||||
|
# applications related to the deployment of airbags, or any
|
||||||
|
# other applications that could lead to death, personal
|
||||||
|
# injury, or severe property or environmental damage
|
||||||
|
# (individually and collectively, "Critical
|
||||||
|
# Applications"). Customer assumes the sole risk and
|
||||||
|
# liability of any use of AMD products in Critical
|
||||||
|
# Applications, subject only to applicable laws and
|
||||||
|
# regulations governing limitations on product liability.
|
||||||
|
#
|
||||||
|
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||||
|
# PART OF THIS FILE AT ALL TIMES.
|
||||||
|
|
||||||
|
#################
|
||||||
|
#DEFAULT CLOCK CONSTRAINTS
|
||||||
|
|
||||||
|
############################################################
|
||||||
|
# Clock Period Constraints #
|
||||||
|
############################################################
|
||||||
|
#create_clock -period 10.000 [get_ports clk_in1]
|
||||||
|
|
||||||
@@ -0,0 +1,220 @@
|
|||||||
|
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||||
|
// Date : Tue Jul 9 23:44:24 2024
|
||||||
|
// Host : Viviana running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode funcsim
|
||||||
|
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
|
||||||
|
// Design : phase_locked_loop
|
||||||
|
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||||
|
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||||
|
// Device : xc7a35tfgg484-1
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
(* NotValidForBitStream *)
|
||||||
|
module phase_locked_loop
|
||||||
|
(clk_out1,
|
||||||
|
reset,
|
||||||
|
locked,
|
||||||
|
clk_in1);
|
||||||
|
output clk_out1;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
|
||||||
|
(* IBUF_LOW_PWR *) wire clk_in1;
|
||||||
|
wire clk_out1;
|
||||||
|
wire locked;
|
||||||
|
wire reset;
|
||||||
|
|
||||||
|
phase_locked_loop_clk_wiz inst
|
||||||
|
(.clk_in1(clk_in1),
|
||||||
|
.clk_out1(clk_out1),
|
||||||
|
.locked(locked),
|
||||||
|
.reset(reset));
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
module phase_locked_loop_clk_wiz
|
||||||
|
(clk_out1,
|
||||||
|
reset,
|
||||||
|
locked,
|
||||||
|
clk_in1);
|
||||||
|
output clk_out1;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
|
||||||
|
wire clk_in1;
|
||||||
|
wire clk_in1_phase_locked_loop;
|
||||||
|
wire clk_out1;
|
||||||
|
wire clk_out1_phase_locked_loop;
|
||||||
|
wire clkfbout_buf_phase_locked_loop;
|
||||||
|
wire clkfbout_phase_locked_loop;
|
||||||
|
wire locked;
|
||||||
|
wire reset;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED;
|
||||||
|
wire NLW_plle2_adv_inst_DRDY_UNCONNECTED;
|
||||||
|
wire [15:0]NLW_plle2_adv_inst_DO_UNCONNECTED;
|
||||||
|
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
BUFG clkf_buf
|
||||||
|
(.I(clkfbout_phase_locked_loop),
|
||||||
|
.O(clkfbout_buf_phase_locked_loop));
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
(* CAPACITANCE = "DONT_CARE" *)
|
||||||
|
(* IBUF_DELAY_VALUE = "0" *)
|
||||||
|
(* IFD_DELAY_VALUE = "AUTO" *)
|
||||||
|
IBUF #(
|
||||||
|
.IOSTANDARD("DEFAULT"))
|
||||||
|
clkin1_ibufg
|
||||||
|
(.I(clk_in1),
|
||||||
|
.O(clk_in1_phase_locked_loop));
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
BUFG clkout1_buf
|
||||||
|
(.I(clk_out1_phase_locked_loop),
|
||||||
|
.O(clk_out1));
|
||||||
|
(* BOX_TYPE = "PRIMITIVE" *)
|
||||||
|
PLLE2_ADV #(
|
||||||
|
.BANDWIDTH("OPTIMIZED"),
|
||||||
|
.CLKFBOUT_MULT(41),
|
||||||
|
.CLKFBOUT_PHASE(0.000000),
|
||||||
|
.CLKIN1_PERIOD(10.000000),
|
||||||
|
.CLKIN2_PERIOD(0.000000),
|
||||||
|
.CLKOUT0_DIVIDE(82),
|
||||||
|
.CLKOUT0_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT0_PHASE(0.000000),
|
||||||
|
.CLKOUT1_DIVIDE(1),
|
||||||
|
.CLKOUT1_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT1_PHASE(0.000000),
|
||||||
|
.CLKOUT2_DIVIDE(1),
|
||||||
|
.CLKOUT2_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT2_PHASE(0.000000),
|
||||||
|
.CLKOUT3_DIVIDE(1),
|
||||||
|
.CLKOUT3_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT3_PHASE(0.000000),
|
||||||
|
.CLKOUT4_DIVIDE(1),
|
||||||
|
.CLKOUT4_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT4_PHASE(0.000000),
|
||||||
|
.CLKOUT5_DIVIDE(1),
|
||||||
|
.CLKOUT5_DUTY_CYCLE(0.500000),
|
||||||
|
.CLKOUT5_PHASE(0.000000),
|
||||||
|
.COMPENSATION("ZHOLD"),
|
||||||
|
.DIVCLK_DIVIDE(5),
|
||||||
|
.IS_CLKINSEL_INVERTED(1'b0),
|
||||||
|
.IS_PWRDWN_INVERTED(1'b0),
|
||||||
|
.IS_RST_INVERTED(1'b0),
|
||||||
|
.REF_JITTER1(0.010000),
|
||||||
|
.REF_JITTER2(0.010000),
|
||||||
|
.STARTUP_WAIT("FALSE"))
|
||||||
|
plle2_adv_inst
|
||||||
|
(.CLKFBIN(clkfbout_buf_phase_locked_loop),
|
||||||
|
.CLKFBOUT(clkfbout_phase_locked_loop),
|
||||||
|
.CLKIN1(clk_in1_phase_locked_loop),
|
||||||
|
.CLKIN2(1'b0),
|
||||||
|
.CLKINSEL(1'b1),
|
||||||
|
.CLKOUT0(clk_out1_phase_locked_loop),
|
||||||
|
.CLKOUT1(NLW_plle2_adv_inst_CLKOUT1_UNCONNECTED),
|
||||||
|
.CLKOUT2(NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED),
|
||||||
|
.CLKOUT3(NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED),
|
||||||
|
.CLKOUT4(NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED),
|
||||||
|
.CLKOUT5(NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED),
|
||||||
|
.DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.DCLK(1'b0),
|
||||||
|
.DEN(1'b0),
|
||||||
|
.DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||||
|
.DO(NLW_plle2_adv_inst_DO_UNCONNECTED[15:0]),
|
||||||
|
.DRDY(NLW_plle2_adv_inst_DRDY_UNCONNECTED),
|
||||||
|
.DWE(1'b0),
|
||||||
|
.LOCKED(locked),
|
||||||
|
.PWRDWN(1'b0),
|
||||||
|
.RST(reset));
|
||||||
|
endmodule
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
parameter GRES_WIDTH = 10000;
|
||||||
|
parameter GRES_START = 10000;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
wire GRESTORE;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
reg GRESTORE_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
#(GRES_START);
|
||||||
|
GRESTORE_int = 1'b1;
|
||||||
|
#(GRES_WIDTH);
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
@@ -0,0 +1,24 @@
|
|||||||
|
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||||
|
// Date : Tue Jul 9 23:44:24 2024
|
||||||
|
// Host : Viviana running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
|
||||||
|
// Design : phase_locked_loop
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7a35tfgg484-1
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
module phase_locked_loop(clk_out1, reset, locked, clk_in1)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
|
||||||
|
/* synthesis syn_force_seq_prim="clk_out1" */;
|
||||||
|
output clk_out1 /* synthesis syn_isclock = 1 */;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
endmodule
|
||||||
1
PipelineProcessor.ip_user_files/README.txt
Normal file
1
PipelineProcessor.ip_user_files/README.txt
Normal file
@@ -0,0 +1 @@
|
|||||||
|
The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
|
||||||
@@ -0,0 +1,24 @@
|
|||||||
|
// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||||
|
// Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
// Tool Version: Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||||
|
// Date : Tue Jul 9 23:44:24 2024
|
||||||
|
// Host : Viviana running 64-bit major release (build 9200)
|
||||||
|
// Command : write_verilog -force -mode synth_stub
|
||||||
|
// d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
|
||||||
|
// Design : phase_locked_loop
|
||||||
|
// Purpose : Stub declaration of top-level module interface
|
||||||
|
// Device : xc7a35tfgg484-1
|
||||||
|
// --------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||||
|
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||||
|
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||||
|
module phase_locked_loop(clk_out1, reset, locked, clk_in1)
|
||||||
|
/* synthesis syn_black_box black_box_pad_pin="reset,locked,clk_in1" */
|
||||||
|
/* synthesis syn_force_seq_prim="clk_out1" */;
|
||||||
|
output clk_out1 /* synthesis syn_isclock = 1 */;
|
||||||
|
input reset;
|
||||||
|
output locked;
|
||||||
|
input clk_in1;
|
||||||
|
endmodule
|
||||||
@@ -0,0 +1,50 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2023.2 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and how to fetch design source file details
|
||||||
|
# from the file_info.txt file.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. Steps to run the generated simulation script
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./phase_locked_loop.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||||
|
is to verify the generated script arguments and print error if incorrect switch
|
||||||
|
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||||
|
which is to specify custom or initialization commands. The function also executes
|
||||||
|
following sub-functions:-
|
||||||
|
'reset_run' if -reset_run switch is specified.
|
||||||
|
'reset_log' if -reset_log switch is specified.
|
||||||
|
|
||||||
|
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||||
|
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||||
|
the simulator generated log files.
|
||||||
|
|
||||||
|
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||||
|
create design library mappings and directories. This function is called before the
|
||||||
|
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||||
|
script will execute that specfic step, else it will execute all steps applicable
|
||||||
|
for the target simulator.
|
||||||
|
|
||||||
|
For more information on the script, please type './phase_locked_loop.sh -help'
|
||||||
|
|
||||||
|
2. Design source file information
|
||||||
|
|
||||||
|
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||||
|
based on the compile order when export_simulation was executed from Vivado. The file
|
||||||
|
contains information about the file name, type, library it is compiled into, whether
|
||||||
|
it is part of the IP, associated library, file path information in a comma separated
|
||||||
|
format. This file can be parsed to extract the required information for generating a
|
||||||
|
custom script or can be read from verification test infra.
|
||||||
|
|
||||||
@@ -0,0 +1,5 @@
|
|||||||
|
xpm_cdc.sv,systemverilog,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
xpm_VCOMP.vhd,vhdl,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop_clk_wiz.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
@@ -0,0 +1,84 @@
|
|||||||
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
parameter GRES_WIDTH = 10000;
|
||||||
|
parameter GRES_START = 10000;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
wire GRESTORE;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
reg GRESTORE_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
#(GRES_START);
|
||||||
|
GRESTORE_int = 1'b1;
|
||||||
|
#(GRES_WIDTH);
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
@@ -0,0 +1,50 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2023.2 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and how to fetch design source file details
|
||||||
|
# from the file_info.txt file.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. Steps to run the generated simulation script
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./phase_locked_loop.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||||
|
is to verify the generated script arguments and print error if incorrect switch
|
||||||
|
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||||
|
which is to specify custom or initialization commands. The function also executes
|
||||||
|
following sub-functions:-
|
||||||
|
'reset_run' if -reset_run switch is specified.
|
||||||
|
'reset_log' if -reset_log switch is specified.
|
||||||
|
|
||||||
|
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||||
|
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||||
|
the simulator generated log files.
|
||||||
|
|
||||||
|
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||||
|
create design library mappings and directories. This function is called before the
|
||||||
|
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||||
|
script will execute that specfic step, else it will execute all steps applicable
|
||||||
|
for the target simulator.
|
||||||
|
|
||||||
|
For more information on the script, please type './phase_locked_loop.sh -help'
|
||||||
|
|
||||||
|
2. Design source file information
|
||||||
|
|
||||||
|
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||||
|
based on the compile order when export_simulation was executed from Vivado. The file
|
||||||
|
contains information about the file name, type, library it is compiled into, whether
|
||||||
|
it is part of the IP, associated library, file path information in a comma separated
|
||||||
|
format. This file can be parsed to extract the required information for generating a
|
||||||
|
custom script or can be read from verification test infra.
|
||||||
|
|
||||||
@@ -0,0 +1,5 @@
|
|||||||
|
xpm_cdc.sv,systemverilog,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
xpm_VCOMP.vhd,vhdl,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop_clk_wiz.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
@@ -0,0 +1,84 @@
|
|||||||
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
parameter GRES_WIDTH = 10000;
|
||||||
|
parameter GRES_START = 10000;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
wire GRESTORE;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
reg GRESTORE_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
#(GRES_START);
|
||||||
|
GRESTORE_int = 1'b1;
|
||||||
|
#(GRES_WIDTH);
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
@@ -0,0 +1,50 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2023.2 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and how to fetch design source file details
|
||||||
|
# from the file_info.txt file.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. Steps to run the generated simulation script
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./phase_locked_loop.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||||
|
is to verify the generated script arguments and print error if incorrect switch
|
||||||
|
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||||
|
which is to specify custom or initialization commands. The function also executes
|
||||||
|
following sub-functions:-
|
||||||
|
'reset_run' if -reset_run switch is specified.
|
||||||
|
'reset_log' if -reset_log switch is specified.
|
||||||
|
|
||||||
|
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||||
|
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||||
|
the simulator generated log files.
|
||||||
|
|
||||||
|
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||||
|
create design library mappings and directories. This function is called before the
|
||||||
|
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||||
|
script will execute that specfic step, else it will execute all steps applicable
|
||||||
|
for the target simulator.
|
||||||
|
|
||||||
|
For more information on the script, please type './phase_locked_loop.sh -help'
|
||||||
|
|
||||||
|
2. Design source file information
|
||||||
|
|
||||||
|
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||||
|
based on the compile order when export_simulation was executed from Vivado. The file
|
||||||
|
contains information about the file name, type, library it is compiled into, whether
|
||||||
|
it is part of the IP, associated library, file path information in a comma separated
|
||||||
|
format. This file can be parsed to extract the required information for generating a
|
||||||
|
custom script or can be read from verification test infra.
|
||||||
|
|
||||||
@@ -0,0 +1,5 @@
|
|||||||
|
xpm_cdc.sv,systemverilog,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
xpm_VCOMP.vhd,vhdl,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop_clk_wiz.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
@@ -0,0 +1,84 @@
|
|||||||
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
parameter GRES_WIDTH = 10000;
|
||||||
|
parameter GRES_START = 10000;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
wire GRESTORE;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
reg GRESTORE_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
#(GRES_START);
|
||||||
|
GRESTORE_int = 1'b1;
|
||||||
|
#(GRES_WIDTH);
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
@@ -0,0 +1,50 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2023.2 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and how to fetch design source file details
|
||||||
|
# from the file_info.txt file.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. Steps to run the generated simulation script
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./phase_locked_loop.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||||
|
is to verify the generated script arguments and print error if incorrect switch
|
||||||
|
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||||
|
which is to specify custom or initialization commands. The function also executes
|
||||||
|
following sub-functions:-
|
||||||
|
'reset_run' if -reset_run switch is specified.
|
||||||
|
'reset_log' if -reset_log switch is specified.
|
||||||
|
|
||||||
|
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||||
|
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||||
|
the simulator generated log files.
|
||||||
|
|
||||||
|
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||||
|
create design library mappings and directories. This function is called before the
|
||||||
|
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||||
|
script will execute that specfic step, else it will execute all steps applicable
|
||||||
|
for the target simulator.
|
||||||
|
|
||||||
|
For more information on the script, please type './phase_locked_loop.sh -help'
|
||||||
|
|
||||||
|
2. Design source file information
|
||||||
|
|
||||||
|
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||||
|
based on the compile order when export_simulation was executed from Vivado. The file
|
||||||
|
contains information about the file name, type, library it is compiled into, whether
|
||||||
|
it is part of the IP, associated library, file path information in a comma separated
|
||||||
|
format. This file can be parsed to extract the required information for generating a
|
||||||
|
custom script or can be read from verification test infra.
|
||||||
|
|
||||||
@@ -0,0 +1,5 @@
|
|||||||
|
xpm_cdc.sv,systemverilog,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
xpm_VCOMP.vhd,vhdl,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop_clk_wiz.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
@@ -0,0 +1,84 @@
|
|||||||
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
parameter GRES_WIDTH = 10000;
|
||||||
|
parameter GRES_START = 10000;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
wire GRESTORE;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
reg GRESTORE_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
#(GRES_START);
|
||||||
|
GRESTORE_int = 1'b1;
|
||||||
|
#(GRES_WIDTH);
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
@@ -0,0 +1,50 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2023.2 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and how to fetch design source file details
|
||||||
|
# from the file_info.txt file.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. Steps to run the generated simulation script
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./phase_locked_loop.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||||
|
is to verify the generated script arguments and print error if incorrect switch
|
||||||
|
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||||
|
which is to specify custom or initialization commands. The function also executes
|
||||||
|
following sub-functions:-
|
||||||
|
'reset_run' if -reset_run switch is specified.
|
||||||
|
'reset_log' if -reset_log switch is specified.
|
||||||
|
|
||||||
|
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||||
|
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||||
|
the simulator generated log files.
|
||||||
|
|
||||||
|
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||||
|
create design library mappings and directories. This function is called before the
|
||||||
|
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||||
|
script will execute that specfic step, else it will execute all steps applicable
|
||||||
|
for the target simulator.
|
||||||
|
|
||||||
|
For more information on the script, please type './phase_locked_loop.sh -help'
|
||||||
|
|
||||||
|
2. Design source file information
|
||||||
|
|
||||||
|
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||||
|
based on the compile order when export_simulation was executed from Vivado. The file
|
||||||
|
contains information about the file name, type, library it is compiled into, whether
|
||||||
|
it is part of the IP, associated library, file path information in a comma separated
|
||||||
|
format. This file can be parsed to extract the required information for generating a
|
||||||
|
custom script or can be read from verification test infra.
|
||||||
|
|
||||||
@@ -0,0 +1,5 @@
|
|||||||
|
xpm_cdc.sv,systemverilog,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
xpm_VCOMP.vhd,vhdl,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop_clk_wiz.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
@@ -0,0 +1,84 @@
|
|||||||
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
parameter GRES_WIDTH = 10000;
|
||||||
|
parameter GRES_START = 10000;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
wire GRESTORE;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
reg GRESTORE_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
#(GRES_START);
|
||||||
|
GRESTORE_int = 1'b1;
|
||||||
|
#(GRES_WIDTH);
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
@@ -0,0 +1,50 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2023.2 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and how to fetch design source file details
|
||||||
|
# from the file_info.txt file.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. Steps to run the generated simulation script
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./phase_locked_loop.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||||
|
is to verify the generated script arguments and print error if incorrect switch
|
||||||
|
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||||
|
which is to specify custom or initialization commands. The function also executes
|
||||||
|
following sub-functions:-
|
||||||
|
'reset_run' if -reset_run switch is specified.
|
||||||
|
'reset_log' if -reset_log switch is specified.
|
||||||
|
|
||||||
|
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||||
|
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||||
|
the simulator generated log files.
|
||||||
|
|
||||||
|
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||||
|
create design library mappings and directories. This function is called before the
|
||||||
|
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||||
|
script will execute that specfic step, else it will execute all steps applicable
|
||||||
|
for the target simulator.
|
||||||
|
|
||||||
|
For more information on the script, please type './phase_locked_loop.sh -help'
|
||||||
|
|
||||||
|
2. Design source file information
|
||||||
|
|
||||||
|
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||||
|
based on the compile order when export_simulation was executed from Vivado. The file
|
||||||
|
contains information about the file name, type, library it is compiled into, whether
|
||||||
|
it is part of the IP, associated library, file path information in a comma separated
|
||||||
|
format. This file can be parsed to extract the required information for generating a
|
||||||
|
custom script or can be read from verification test infra.
|
||||||
|
|
||||||
@@ -0,0 +1,5 @@
|
|||||||
|
xpm_cdc.sv,systemverilog,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
xpm_VCOMP.vhd,vhdl,xpm,E:/Applications/Xilinx/Vivado/2023.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop_clk_wiz.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
@@ -0,0 +1,84 @@
|
|||||||
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
parameter GRES_WIDTH = 10000;
|
||||||
|
parameter GRES_START = 10000;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
wire GRESTORE;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
reg GRESTORE_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
#(GRES_START);
|
||||||
|
GRESTORE_int = 1'b1;
|
||||||
|
#(GRES_WIDTH);
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
@@ -0,0 +1,50 @@
|
|||||||
|
################################################################################
|
||||||
|
# Vivado (TM) v2023.2 (64-bit)
|
||||||
|
#
|
||||||
|
# README.txt: Please read the sections below to understand the steps required to
|
||||||
|
# run the exported script and how to fetch design source file details
|
||||||
|
# from the file_info.txt file.
|
||||||
|
#
|
||||||
|
# Generated by export_simulation on Tue Jul 09 23:43:41 +0800 2024
|
||||||
|
#
|
||||||
|
################################################################################
|
||||||
|
|
||||||
|
1. Steps to run the generated simulation script
|
||||||
|
|
||||||
|
From the shell prompt in the current directory, issue the following command:-
|
||||||
|
|
||||||
|
./phase_locked_loop.sh
|
||||||
|
|
||||||
|
This command will launch the 'compile', 'elaborate' and 'simulate' functions
|
||||||
|
implemented in the script file for the 3-step flow. These functions are called
|
||||||
|
from the main 'run' function in the script file.
|
||||||
|
|
||||||
|
The 'run' function first calls the 'check_args' function, the purpose of which
|
||||||
|
is to verify the generated script arguments and print error if incorrect switch
|
||||||
|
is specified. The 'run' function then calls the 'setup' function, the purpose of
|
||||||
|
which is to specify custom or initialization commands. The function also executes
|
||||||
|
following sub-functions:-
|
||||||
|
'reset_run' if -reset_run switch is specified.
|
||||||
|
'reset_log' if -reset_log switch is specified.
|
||||||
|
|
||||||
|
The purpose of 'reset_run' function' is to delete the simulator generated design
|
||||||
|
data from the previous run and the purpose of 'reset_log' function' is to delete
|
||||||
|
the simulator generated log files.
|
||||||
|
|
||||||
|
The 'run' function then calls the 'init_lib' function, the purpose of which is to
|
||||||
|
create design library mappings and directories. This function is called before the
|
||||||
|
'compile' step. By default, if '-step' switch is specified with the script then the
|
||||||
|
script will execute that specfic step, else it will execute all steps applicable
|
||||||
|
for the target simulator.
|
||||||
|
|
||||||
|
For more information on the script, please type './phase_locked_loop.sh -help'
|
||||||
|
|
||||||
|
2. Design source file information
|
||||||
|
|
||||||
|
export_simulation generates a 'file_info.txt' file that contains design file information
|
||||||
|
based on the compile order when export_simulation was executed from Vivado. The file
|
||||||
|
contains information about the file name, type, library it is compiled into, whether
|
||||||
|
it is part of the IP, associated library, file path information in a comma separated
|
||||||
|
format. This file can be parsed to extract the required information for generating a
|
||||||
|
custom script or can be read from verification test infra.
|
||||||
|
|
||||||
@@ -0,0 +1,12 @@
|
|||||||
|
set curr_wave [current_wave_config]
|
||||||
|
if { [string length $curr_wave] == 0 } {
|
||||||
|
if { [llength [get_objects]] > 0} {
|
||||||
|
add_wave /
|
||||||
|
set_property needs_save false [current_wave_config]
|
||||||
|
} else {
|
||||||
|
send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
run 1000ns
|
||||||
|
quit
|
||||||
@@ -0,0 +1,3 @@
|
|||||||
|
phase_locked_loop_clk_wiz.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
phase_locked_loop.v,verilog,xil_defaultlib,../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v,incdir="../../../ipstatic"incdir="../../../ipstatic"
|
||||||
|
glbl.v,Verilog,xil_defaultlib,glbl.v
|
||||||
@@ -0,0 +1,84 @@
|
|||||||
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
|
||||||
|
`ifndef GLBL
|
||||||
|
`define GLBL
|
||||||
|
`timescale 1 ps / 1 ps
|
||||||
|
|
||||||
|
module glbl ();
|
||||||
|
|
||||||
|
parameter ROC_WIDTH = 100000;
|
||||||
|
parameter TOC_WIDTH = 0;
|
||||||
|
parameter GRES_WIDTH = 10000;
|
||||||
|
parameter GRES_START = 10000;
|
||||||
|
|
||||||
|
//-------- STARTUP Globals --------------
|
||||||
|
wire GSR;
|
||||||
|
wire GTS;
|
||||||
|
wire GWE;
|
||||||
|
wire PRLD;
|
||||||
|
wire GRESTORE;
|
||||||
|
tri1 p_up_tmp;
|
||||||
|
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||||
|
|
||||||
|
wire PROGB_GLBL;
|
||||||
|
wire CCLKO_GLBL;
|
||||||
|
wire FCSBO_GLBL;
|
||||||
|
wire [3:0] DO_GLBL;
|
||||||
|
wire [3:0] DI_GLBL;
|
||||||
|
|
||||||
|
reg GSR_int;
|
||||||
|
reg GTS_int;
|
||||||
|
reg PRLD_int;
|
||||||
|
reg GRESTORE_int;
|
||||||
|
|
||||||
|
//-------- JTAG Globals --------------
|
||||||
|
wire JTAG_TDO_GLBL;
|
||||||
|
wire JTAG_TCK_GLBL;
|
||||||
|
wire JTAG_TDI_GLBL;
|
||||||
|
wire JTAG_TMS_GLBL;
|
||||||
|
wire JTAG_TRST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_CAPTURE_GLBL;
|
||||||
|
reg JTAG_RESET_GLBL;
|
||||||
|
reg JTAG_SHIFT_GLBL;
|
||||||
|
reg JTAG_UPDATE_GLBL;
|
||||||
|
reg JTAG_RUNTEST_GLBL;
|
||||||
|
|
||||||
|
reg JTAG_SEL1_GLBL = 0;
|
||||||
|
reg JTAG_SEL2_GLBL = 0 ;
|
||||||
|
reg JTAG_SEL3_GLBL = 0;
|
||||||
|
reg JTAG_SEL4_GLBL = 0;
|
||||||
|
|
||||||
|
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||||
|
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||||
|
|
||||||
|
assign (strong1, weak0) GSR = GSR_int;
|
||||||
|
assign (strong1, weak0) GTS = GTS_int;
|
||||||
|
assign (weak1, weak0) PRLD = PRLD_int;
|
||||||
|
assign (strong1, weak0) GRESTORE = GRESTORE_int;
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GSR_int = 1'b1;
|
||||||
|
PRLD_int = 1'b1;
|
||||||
|
#(ROC_WIDTH)
|
||||||
|
GSR_int = 1'b0;
|
||||||
|
PRLD_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GTS_int = 1'b1;
|
||||||
|
#(TOC_WIDTH)
|
||||||
|
GTS_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
initial begin
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
#(GRES_START);
|
||||||
|
GRESTORE_int = 1'b1;
|
||||||
|
#(GRES_WIDTH);
|
||||||
|
GRESTORE_int = 1'b0;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
`endif
|
||||||
@@ -0,0 +1,8 @@
|
|||||||
|
verilog xil_defaultlib --include "../../../ipstatic" \
|
||||||
|
"../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v" \
|
||||||
|
"../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v" \
|
||||||
|
|
||||||
|
verilog xil_defaultlib "glbl.v"
|
||||||
|
|
||||||
|
# Do not sort compile order
|
||||||
|
nosort
|
||||||
@@ -0,0 +1,4 @@
|
|||||||
|
set_property SRC_FILE_INFO {cfile:d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc rfile:../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc id:1 order:EARLY scoped_inst:inst} [current_design]
|
||||||
|
current_instance inst
|
||||||
|
set_property src_info {type:SCOPED_XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design]
|
||||||
|
set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100
|
||||||
@@ -0,0 +1,32 @@
|
|||||||
|
# This file is automatically generated.
|
||||||
|
# It contains project source information necessary for synthesis and implementation.
|
||||||
|
|
||||||
|
# IP: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||||
|
# IP: The module: 'phase_locked_loop' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||||
|
|
||||||
|
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc
|
||||||
|
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
|
||||||
|
set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||||
|
|
||||||
|
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc
|
||||||
|
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
|
||||||
|
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||||
|
|
||||||
|
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc
|
||||||
|
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
|
||||||
|
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||||
|
|
||||||
|
# IP: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||||
|
# IP: The module: 'phase_locked_loop' is the root of the design. Do not add the DONT_TOUCH constraint.
|
||||||
|
|
||||||
|
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc
|
||||||
|
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
|
||||||
|
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||||
|
|
||||||
|
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc
|
||||||
|
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
|
||||||
|
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||||
|
|
||||||
|
# XDC: d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc
|
||||||
|
# XDC: The top module name and the constraint reference have the same name: 'phase_locked_loop'. Do not add the DONT_TOUCH constraint.
|
||||||
|
#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
|
||||||
10
PipelineProcessor.runs/phase_locked_loop_synth_1/htr.txt
Normal file
10
PipelineProcessor.runs/phase_locked_loop_synth_1/htr.txt
Normal file
@@ -0,0 +1,10 @@
|
|||||||
|
REM
|
||||||
|
REM Vivado(TM)
|
||||||
|
REM htr.txt: a Vivado-generated description of how-to-repeat the
|
||||||
|
REM the basic steps of a run. Note that runme.bat/sh needs
|
||||||
|
REM to be invoked for Vivado to track run status.
|
||||||
|
REM Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||||
|
REM Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||||
|
REM
|
||||||
|
|
||||||
|
vivado -log phase_locked_loop.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl
|
||||||
Binary file not shown.
@@ -0,0 +1,246 @@
|
|||||||
|
#
|
||||||
|
# Synthesis run script generated by Vivado
|
||||||
|
#
|
||||||
|
|
||||||
|
set TIME_start [clock seconds]
|
||||||
|
namespace eval ::optrace {
|
||||||
|
variable script "D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.tcl"
|
||||||
|
variable category "vivado_synth"
|
||||||
|
}
|
||||||
|
|
||||||
|
# Try to connect to running dispatch if we haven't done so already.
|
||||||
|
# This code assumes that the Tcl interpreter is not using threads,
|
||||||
|
# since the ::dispatch::connected variable isn't mutex protected.
|
||||||
|
if {![info exists ::dispatch::connected]} {
|
||||||
|
namespace eval ::dispatch {
|
||||||
|
variable connected false
|
||||||
|
if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
|
||||||
|
set result "true"
|
||||||
|
if {[catch {
|
||||||
|
if {[lsearch -exact [package names] DispatchTcl] < 0} {
|
||||||
|
set result [load librdi_cd_clienttcl[info sharedlibextension]]
|
||||||
|
}
|
||||||
|
if {$result eq "false"} {
|
||||||
|
puts "WARNING: Could not load dispatch client library"
|
||||||
|
}
|
||||||
|
set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
|
||||||
|
if { $connect_id eq "" } {
|
||||||
|
puts "WARNING: Could not initialize dispatch client"
|
||||||
|
} else {
|
||||||
|
puts "INFO: Dispatch client connection id - $connect_id"
|
||||||
|
set connected true
|
||||||
|
}
|
||||||
|
} catch_res]} {
|
||||||
|
puts "WARNING: failed to connect to dispatch server - $catch_res"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
if {$::dispatch::connected} {
|
||||||
|
# Remove the dummy proc if it exists.
|
||||||
|
if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
|
||||||
|
rename ::OPTRACE ""
|
||||||
|
}
|
||||||
|
proc ::OPTRACE { task action {tags {} } } {
|
||||||
|
::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
|
||||||
|
}
|
||||||
|
# dispatch is generic. We specifically want to attach logging.
|
||||||
|
::vitis_log::connect_client
|
||||||
|
} else {
|
||||||
|
# Add dummy proc if it doesn't exist.
|
||||||
|
if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
|
||||||
|
proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
|
||||||
|
# Do nothing
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
proc create_report { reportName command } {
|
||||||
|
set status "."
|
||||||
|
append status $reportName ".fail"
|
||||||
|
if { [file exists $status] } {
|
||||||
|
eval file delete [glob $status]
|
||||||
|
}
|
||||||
|
send_msg_id runtcl-4 info "Executing : $command"
|
||||||
|
set retval [eval catch { $command } msg]
|
||||||
|
if { $retval != 0 } {
|
||||||
|
set fp [open $status w]
|
||||||
|
close $fp
|
||||||
|
send_msg_id runtcl-5 warning "$msg"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
OPTRACE "phase_locked_loop_synth_1" START { ROLLUP_AUTO }
|
||||||
|
set_param project.vivado.isBlockSynthRun true
|
||||||
|
set_msg_config -msgmgr_mode ooc_run
|
||||||
|
OPTRACE "Creating in-memory project" START { }
|
||||||
|
create_project -in_memory -part xc7a35tfgg484-1
|
||||||
|
|
||||||
|
set_param project.singleFileAddWarning.threshold 0
|
||||||
|
set_param project.compositeFile.enableAutoGeneration 0
|
||||||
|
set_param synth.vivado.isSynthRun true
|
||||||
|
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
|
||||||
|
set_property webtalk.parent_dir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/wt [current_project]
|
||||||
|
set_property parent.project_path D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.xpr [current_project]
|
||||||
|
set_property XPM_LIBRARIES XPM_CDC [current_project]
|
||||||
|
set_property default_lib xil_defaultlib [current_project]
|
||||||
|
set_property target_language Verilog [current_project]
|
||||||
|
set_property ip_output_repo d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.cache/ip [current_project]
|
||||||
|
set_property ip_cache_permissions {read write} [current_project]
|
||||||
|
OPTRACE "Creating in-memory project" END { }
|
||||||
|
OPTRACE "Adding files" START { }
|
||||||
|
read_ip -quiet d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.srcs/sources_1/ip/phase_locked_loop/phase_locked_loop.xci
|
||||||
|
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc]
|
||||||
|
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc]
|
||||||
|
set_property used_in_implementation false [get_files -all d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc]
|
||||||
|
|
||||||
|
OPTRACE "Adding files" END { }
|
||||||
|
# Mark all dcp files as not used in implementation to prevent them from being
|
||||||
|
# stitched into the results of this synthesis run. Any black boxes in the
|
||||||
|
# design are intentionally left as such for best results. Dcp files will be
|
||||||
|
# stitched into the design at a later time, either when this synthesis run is
|
||||||
|
# opened, or when it is stitched into a dependent implementation run.
|
||||||
|
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
|
||||||
|
set_property used_in_implementation false $dcp
|
||||||
|
}
|
||||||
|
read_xdc dont_touch.xdc
|
||||||
|
set_property used_in_implementation false [get_files dont_touch.xdc]
|
||||||
|
set_param ips.enableIPCacheLiteLoad 1
|
||||||
|
OPTRACE "Configure IP Cache" START { }
|
||||||
|
|
||||||
|
set cacheID [config_ip_cache -export -no_bom -dir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1 -new_name phase_locked_loop -ip [get_ips phase_locked_loop]]
|
||||||
|
|
||||||
|
OPTRACE "Configure IP Cache" END { }
|
||||||
|
if { $cacheID == "" } {
|
||||||
|
close [open __synthesis_is_running__ w]
|
||||||
|
|
||||||
|
OPTRACE "synth_design" START { }
|
||||||
|
synth_design -top phase_locked_loop -part xc7a35tfgg484-1 -incremental_mode off -mode out_of_context
|
||||||
|
OPTRACE "synth_design" END { }
|
||||||
|
OPTRACE "Write IP Cache" START { }
|
||||||
|
|
||||||
|
#---------------------------------------------------------
|
||||||
|
# Generate Checkpoint/Stub/Simulation Files For IP Cache
|
||||||
|
#---------------------------------------------------------
|
||||||
|
# disable binary constraint mode for IPCache checkpoints
|
||||||
|
set_param constraints.enableBinaryConstraints false
|
||||||
|
|
||||||
|
catch {
|
||||||
|
write_checkpoint -force -noxdef -rename_prefix phase_locked_loop_ phase_locked_loop.dcp
|
||||||
|
|
||||||
|
set ipCachedFiles {}
|
||||||
|
write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.v
|
||||||
|
lappend ipCachedFiles phase_locked_loop_stub.v
|
||||||
|
|
||||||
|
write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_stub.vhdl
|
||||||
|
lappend ipCachedFiles phase_locked_loop_stub.vhdl
|
||||||
|
|
||||||
|
write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.v
|
||||||
|
lappend ipCachedFiles phase_locked_loop_sim_netlist.v
|
||||||
|
|
||||||
|
write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ phase_locked_loop_sim_netlist.vhdl
|
||||||
|
lappend ipCachedFiles phase_locked_loop_sim_netlist.vhdl
|
||||||
|
set TIME_taken [expr [clock seconds] - $TIME_start]
|
||||||
|
|
||||||
|
if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
|
||||||
|
config_ip_cache -add -dcp phase_locked_loop.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips phase_locked_loop]
|
||||||
|
}
|
||||||
|
OPTRACE "Write IP Cache" END { }
|
||||||
|
}
|
||||||
|
if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
|
||||||
|
send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
|
||||||
|
}
|
||||||
|
|
||||||
|
rename_ref -prefix_all phase_locked_loop_
|
||||||
|
|
||||||
|
OPTRACE "write_checkpoint" START { CHECKPOINT }
|
||||||
|
# disable binary constraint mode for synth run checkpoints
|
||||||
|
set_param constraints.enableBinaryConstraints false
|
||||||
|
write_checkpoint -force -noxdef phase_locked_loop.dcp
|
||||||
|
OPTRACE "write_checkpoint" END { }
|
||||||
|
OPTRACE "synth reports" START { REPORT }
|
||||||
|
create_report "phase_locked_loop_synth_1_synth_report_utilization_0" "report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb"
|
||||||
|
OPTRACE "synth reports" END { }
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
file copy -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp
|
||||||
|
} _RESULT ] } {
|
||||||
|
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||||
|
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
write_verilog -force -mode synth_stub d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
|
||||||
|
} _RESULT ] } {
|
||||||
|
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
write_vhdl -force -mode synth_stub d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.vhdl
|
||||||
|
} _RESULT ] } {
|
||||||
|
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
write_verilog -force -mode funcsim d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
|
||||||
|
} _RESULT ] } {
|
||||||
|
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
write_vhdl -force -mode funcsim d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.vhdl
|
||||||
|
} _RESULT ] } {
|
||||||
|
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
} else {
|
||||||
|
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
file copy -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.dcp
|
||||||
|
} _RESULT ] } {
|
||||||
|
send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||||
|
error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_stub.v d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v
|
||||||
|
} _RESULT ] } {
|
||||||
|
puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_stub.vhdl d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.vhdl
|
||||||
|
} _RESULT ] } {
|
||||||
|
puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_sim_netlist.v d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.v
|
||||||
|
} _RESULT ] } {
|
||||||
|
puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||||
|
}
|
||||||
|
|
||||||
|
if { [catch {
|
||||||
|
file rename -force D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop_sim_netlist.vhdl d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_sim_netlist.vhdl
|
||||||
|
} _RESULT ] } {
|
||||||
|
puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
|
||||||
|
}
|
||||||
|
|
||||||
|
close [open .end.used_ip_cache.rst w]
|
||||||
|
}; # end if cacheID
|
||||||
|
|
||||||
|
if {[file isdir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop]} {
|
||||||
|
catch {
|
||||||
|
file copy -force d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.v D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if {[file isdir D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop]} {
|
||||||
|
catch {
|
||||||
|
file copy -force d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_stub.vhdl D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.ip_user_files/ip/phase_locked_loop
|
||||||
|
}
|
||||||
|
}
|
||||||
|
file delete __synthesis_is_running__
|
||||||
|
close [open __synthesis_is_complete__ w]
|
||||||
|
OPTRACE "phase_locked_loop_synth_1" END { }
|
||||||
@@ -0,0 +1,240 @@
|
|||||||
|
#-----------------------------------------------------------
|
||||||
|
# Vivado v2023.2 (64-bit)
|
||||||
|
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
|
||||||
|
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||||
|
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||||
|
# Start of session at: Tue Jul 9 23:43:44 2024
|
||||||
|
# Process ID: 8060
|
||||||
|
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1
|
||||||
|
# Command line: vivado.exe -log phase_locked_loop.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl
|
||||||
|
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds
|
||||||
|
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1\vivado.jou
|
||||||
|
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
|
||||||
|
#-----------------------------------------------------------
|
||||||
|
source phase_locked_loop.tcl -notrace
|
||||||
|
create_project: Time (s): cpu = 00:00:01 ; elapsed = 00:00:09 . Memory (MB): peak = 463.379 ; gain = 184.172
|
||||||
|
INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: phase_locked_loop
|
||||||
|
Command: synth_design -top phase_locked_loop -part xc7a35tfgg484-1 -incremental_mode off -mode out_of_context
|
||||||
|
Starting synth_design
|
||||||
|
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||||
|
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t'
|
||||||
|
INFO: [Device 21-403] Loading part xc7a35tfgg484-1
|
||||||
|
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 2 processes.
|
||||||
|
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
|
||||||
|
INFO: [Synth 8-7075] Helper process launched with PID 32256
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Starting RTL Elaboration : Time (s): cpu = 00:00:01 ; elapsed = 00:00:04 . Memory (MB): peak = 1307.695 ; gain = 439.426
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop' [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v:65]
|
||||||
|
INFO: [Synth 8-6157] synthesizing module 'phase_locked_loop_clk_wiz' [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v:65]
|
||||||
|
INFO: [Synth 8-6157] synthesizing module 'IBUF' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631]
|
||||||
|
INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:73631]
|
||||||
|
INFO: [Synth 8-6157] synthesizing module 'PLLE2_ADV' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351]
|
||||||
|
Parameter BANDWIDTH bound to: OPTIMIZED - type: string
|
||||||
|
Parameter CLKFBOUT_MULT bound to: 41 - type: integer
|
||||||
|
Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
|
||||||
|
Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double
|
||||||
|
Parameter CLKOUT0_DIVIDE bound to: 82 - type: integer
|
||||||
|
Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
|
||||||
|
Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
|
||||||
|
Parameter COMPENSATION bound to: ZHOLD - type: string
|
||||||
|
Parameter DIVCLK_DIVIDE bound to: 5 - type: integer
|
||||||
|
Parameter STARTUP_WAIT bound to: FALSE - type: string
|
||||||
|
INFO: [Synth 8-6155] done synthesizing module 'PLLE2_ADV' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:111351]
|
||||||
|
INFO: [Synth 8-6157] synthesizing module 'BUFG' [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||||
|
INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [E:/Applications/Xilinx/Vivado/2023.2/scripts/rt/data/unisim_comp.v:1951]
|
||||||
|
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop_clk_wiz' (0#1) [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_clk_wiz.v:65]
|
||||||
|
INFO: [Synth 8-6155] done synthesizing module 'phase_locked_loop' (0#1) [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.v:65]
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished RTL Elaboration : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Handling Custom Attributes
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1416.121 ; gain = 0.000
|
||||||
|
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||||
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||||
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||||
|
|
||||||
|
Processing XDC Constraints
|
||||||
|
Initializing timing engine
|
||||||
|
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc] for cell 'inst'
|
||||||
|
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_ooc.xdc] for cell 'inst'
|
||||||
|
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'inst'
|
||||||
|
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop_board.xdc] for cell 'inst'
|
||||||
|
Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'inst'
|
||||||
|
Finished Parsing XDC File [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc] for cell 'inst'
|
||||||
|
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [d:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.gen/sources_1/ip/phase_locked_loop/phase_locked_loop.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/phase_locked_loop_propImpl.xdc].
|
||||||
|
Resolution: To avoid this warning, move constraints listed in [.Xil/phase_locked_loop_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
|
||||||
|
INFO: [Timing 38-2] Deriving generated clocks
|
||||||
|
Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc]
|
||||||
|
Finished Parsing XDC File [D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc]
|
||||||
|
Completed Processing XDC Constraints
|
||||||
|
|
||||||
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1416.121 ; gain = 0.000
|
||||||
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||||
|
No Unisim elements were transformed.
|
||||||
|
|
||||||
|
Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.030 . Memory (MB): peak = 1416.121 ; gain = 0.000
|
||||||
|
INFO: [Designutils 20-5008] Incremental synthesis strategy off
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Constraint Validation : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Loading Part and Timing Information
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Loading part: xc7a35tfgg484-1
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Applying 'set_property' XDC Constraints
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/dont_touch.xdc, line 9).
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:05 ; elapsed = 00:00:11 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:12 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start RTL Component Statistics
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Detailed RTL Component Info :
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished RTL Component Statistics
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Part Resource Summary
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Part Resources:
|
||||||
|
DSPs: 90 (col length:60)
|
||||||
|
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Part Resource Summary
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Cross Boundary and Area Optimization
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:05 ; elapsed = 00:00:13 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Applying XDC Timing Constraints
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Timing Optimization
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Timing Optimization : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Technology Mapping
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Technology Mapping : Time (s): cpu = 00:00:07 ; elapsed = 00:00:17 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start IO Insertion
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Flattening Before IO Insertion
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Flattening Before IO Insertion
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Final Netlist Cleanup
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Final Netlist Cleanup
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished IO Insertion : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Renaming Generated Instances
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Renaming Generated Instances : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Rebuilding User Hierarchy
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Renaming Generated Ports
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Renaming Generated Ports : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Handling Custom Attributes
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Handling Custom Attributes : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Renaming Generated Nets
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Renaming Generated Nets : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Start Writing Synthesis Report
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Report BlackBoxes:
|
||||||
|
+-+--------------+----------+
|
||||||
|
| |BlackBox name |Instances |
|
||||||
|
+-+--------------+----------+
|
||||||
|
+-+--------------+----------+
|
||||||
|
|
||||||
|
Report Cell Usage:
|
||||||
|
+------+----------+------+
|
||||||
|
| |Cell |Count |
|
||||||
|
+------+----------+------+
|
||||||
|
|1 |BUFG | 2|
|
||||||
|
|2 |PLLE2_ADV | 1|
|
||||||
|
|3 |IBUF | 1|
|
||||||
|
+------+----------+------+
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Finished Writing Synthesis Report : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
---------------------------------------------------------------------------------
|
||||||
|
Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
|
||||||
|
Synthesis Optimization Runtime : Time (s): cpu = 00:00:06 ; elapsed = 00:00:19 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
Synthesis Optimization Complete : Time (s): cpu = 00:00:09 ; elapsed = 00:00:20 . Memory (MB): peak = 1416.121 ; gain = 547.852
|
||||||
|
INFO: [Project 1-571] Translating synthesized netlist
|
||||||
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1416.121 ; gain = 0.000
|
||||||
|
INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
|
||||||
|
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
|
||||||
|
INFO: [Project 1-570] Preparing netlist for logic optimization
|
||||||
|
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
|
||||||
|
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1428.094 ; gain = 0.000
|
||||||
|
INFO: [Project 1-111] Unisim Transformation Summary:
|
||||||
|
No Unisim elements were transformed.
|
||||||
|
|
||||||
|
Synth Design complete | Checksum: 5cde1ffc
|
||||||
|
INFO: [Common 17-83] Releasing license: Synthesis
|
||||||
|
30 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
|
||||||
|
synth_design completed successfully
|
||||||
|
synth_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:24 . Memory (MB): peak = 1428.094 ; gain = 952.102
|
||||||
|
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1428.094 ; gain = 0.000
|
||||||
|
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp' has been generated.
|
||||||
|
INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP phase_locked_loop, cache-ID = a4c5028597ba9ab4
|
||||||
|
Write ShapeDB Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1428.094 ; gain = 0.000
|
||||||
|
INFO: [Common 17-1381] The checkpoint 'D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.dcp' has been generated.
|
||||||
|
INFO: [runtcl-4] Executing : report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb
|
||||||
|
INFO: [Common 17-206] Exiting Vivado at Tue Jul 9 23:44:24 2024...
|
||||||
Binary file not shown.
@@ -0,0 +1,175 @@
|
|||||||
|
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
|
||||||
|
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||||
|
| Tool Version : Vivado v.2023.2 (win64) Build 4029153 Fri Oct 13 20:14:34 MDT 2023
|
||||||
|
| Date : Tue Jul 9 23:44:24 2024
|
||||||
|
| Host : Viviana running 64-bit major release (build 9200)
|
||||||
|
| Command : report_utilization -file phase_locked_loop_utilization_synth.rpt -pb phase_locked_loop_utilization_synth.pb
|
||||||
|
| Design : phase_locked_loop
|
||||||
|
| Device : xc7a35tfgg484-1
|
||||||
|
| Speed File : -1
|
||||||
|
| Design State : Synthesized
|
||||||
|
---------------------------------------------------------------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
Utilization Design Information
|
||||||
|
|
||||||
|
Table of Contents
|
||||||
|
-----------------
|
||||||
|
1. Slice Logic
|
||||||
|
1.1 Summary of Registers by Type
|
||||||
|
2. Memory
|
||||||
|
3. DSP
|
||||||
|
4. IO and GT Specific
|
||||||
|
5. Clocking
|
||||||
|
6. Specific Feature
|
||||||
|
7. Primitives
|
||||||
|
8. Black Boxes
|
||||||
|
9. Instantiated Netlists
|
||||||
|
|
||||||
|
1. Slice Logic
|
||||||
|
--------------
|
||||||
|
|
||||||
|
+-------------------------+------+-------+------------+-----------+-------+
|
||||||
|
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||||
|
+-------------------------+------+-------+------------+-----------+-------+
|
||||||
|
| Slice LUTs* | 0 | 0 | 0 | 20800 | 0.00 |
|
||||||
|
| LUT as Logic | 0 | 0 | 0 | 20800 | 0.00 |
|
||||||
|
| LUT as Memory | 0 | 0 | 0 | 9600 | 0.00 |
|
||||||
|
| Slice Registers | 0 | 0 | 0 | 41600 | 0.00 |
|
||||||
|
| Register as Flip Flop | 0 | 0 | 0 | 41600 | 0.00 |
|
||||||
|
| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
|
||||||
|
| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 |
|
||||||
|
| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 |
|
||||||
|
+-------------------------+------+-------+------------+-----------+-------+
|
||||||
|
* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
|
||||||
|
Warning! LUT value is adjusted to account for LUT combining.
|
||||||
|
|
||||||
|
|
||||||
|
1.1 Summary of Registers by Type
|
||||||
|
--------------------------------
|
||||||
|
|
||||||
|
+-------+--------------+-------------+--------------+
|
||||||
|
| Total | Clock Enable | Synchronous | Asynchronous |
|
||||||
|
+-------+--------------+-------------+--------------+
|
||||||
|
| 0 | _ | - | - |
|
||||||
|
| 0 | _ | - | Set |
|
||||||
|
| 0 | _ | - | Reset |
|
||||||
|
| 0 | _ | Set | - |
|
||||||
|
| 0 | _ | Reset | - |
|
||||||
|
| 0 | Yes | - | - |
|
||||||
|
| 0 | Yes | - | Set |
|
||||||
|
| 0 | Yes | - | Reset |
|
||||||
|
| 0 | Yes | Set | - |
|
||||||
|
| 0 | Yes | Reset | - |
|
||||||
|
+-------+--------------+-------------+--------------+
|
||||||
|
|
||||||
|
|
||||||
|
2. Memory
|
||||||
|
---------
|
||||||
|
|
||||||
|
+----------------+------+-------+------------+-----------+-------+
|
||||||
|
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||||
|
+----------------+------+-------+------------+-----------+-------+
|
||||||
|
| Block RAM Tile | 0 | 0 | 0 | 50 | 0.00 |
|
||||||
|
| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
|
||||||
|
| RAMB18 | 0 | 0 | 0 | 100 | 0.00 |
|
||||||
|
+----------------+------+-------+------------+-----------+-------+
|
||||||
|
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
|
||||||
|
|
||||||
|
|
||||||
|
3. DSP
|
||||||
|
------
|
||||||
|
|
||||||
|
+-----------+------+-------+------------+-----------+-------+
|
||||||
|
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||||
|
+-----------+------+-------+------------+-----------+-------+
|
||||||
|
| DSPs | 0 | 0 | 0 | 90 | 0.00 |
|
||||||
|
+-----------+------+-------+------------+-----------+-------+
|
||||||
|
|
||||||
|
|
||||||
|
4. IO and GT Specific
|
||||||
|
---------------------
|
||||||
|
|
||||||
|
+-----------------------------+------+-------+------------+-----------+-------+
|
||||||
|
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||||
|
+-----------------------------+------+-------+------------+-----------+-------+
|
||||||
|
| Bonded IOB | 1 | 0 | 0 | 250 | 0.40 |
|
||||||
|
| Bonded IPADs | 0 | 0 | 0 | 14 | 0.00 |
|
||||||
|
| Bonded OPADs | 0 | 0 | 0 | 8 | 0.00 |
|
||||||
|
| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
|
||||||
|
| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
|
||||||
|
| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
|
||||||
|
| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
|
||||||
|
| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
|
||||||
|
| IBUFDS | 0 | 0 | 0 | 240 | 0.00 |
|
||||||
|
| GTPE2_CHANNEL | 0 | 0 | 0 | 4 | 0.00 |
|
||||||
|
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
|
||||||
|
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
|
||||||
|
| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
|
||||||
|
| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||||
|
| ILOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||||
|
| OLOGIC | 0 | 0 | 0 | 250 | 0.00 |
|
||||||
|
+-----------------------------+------+-------+------------+-----------+-------+
|
||||||
|
|
||||||
|
|
||||||
|
5. Clocking
|
||||||
|
-----------
|
||||||
|
|
||||||
|
+------------+------+-------+------------+-----------+-------+
|
||||||
|
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||||
|
+------------+------+-------+------------+-----------+-------+
|
||||||
|
| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
|
||||||
|
| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
|
||||||
|
| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
|
||||||
|
| PLLE2_ADV | 1 | 0 | 0 | 5 | 20.00 |
|
||||||
|
| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
|
||||||
|
| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
|
||||||
|
| BUFR | 0 | 0 | 0 | 20 | 0.00 |
|
||||||
|
+------------+------+-------+------------+-----------+-------+
|
||||||
|
|
||||||
|
|
||||||
|
6. Specific Feature
|
||||||
|
-------------------
|
||||||
|
|
||||||
|
+-------------+------+-------+------------+-----------+-------+
|
||||||
|
| Site Type | Used | Fixed | Prohibited | Available | Util% |
|
||||||
|
+-------------+------+-------+------------+-----------+-------+
|
||||||
|
| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
|
||||||
|
| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||||
|
| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
|
||||||
|
| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
|
||||||
|
| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||||
|
| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
|
||||||
|
| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
|
||||||
|
| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
|
||||||
|
| XADC | 0 | 0 | 0 | 1 | 0.00 |
|
||||||
|
+-------------+------+-------+------------+-----------+-------+
|
||||||
|
|
||||||
|
|
||||||
|
7. Primitives
|
||||||
|
-------------
|
||||||
|
|
||||||
|
+-----------+------+---------------------+
|
||||||
|
| Ref Name | Used | Functional Category |
|
||||||
|
+-----------+------+---------------------+
|
||||||
|
| BUFG | 2 | Clock |
|
||||||
|
| PLLE2_ADV | 1 | Clock |
|
||||||
|
| IBUF | 1 | IO |
|
||||||
|
+-----------+------+---------------------+
|
||||||
|
|
||||||
|
|
||||||
|
8. Black Boxes
|
||||||
|
--------------
|
||||||
|
|
||||||
|
+----------+------+
|
||||||
|
| Ref Name | Used |
|
||||||
|
+----------+------+
|
||||||
|
|
||||||
|
|
||||||
|
9. Instantiated Netlists
|
||||||
|
------------------------
|
||||||
|
|
||||||
|
+----------+------+
|
||||||
|
| Ref Name | Used |
|
||||||
|
+----------+------+
|
||||||
|
|
||||||
|
|
||||||
14
PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.jou
Normal file
14
PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.jou
Normal file
@@ -0,0 +1,14 @@
|
|||||||
|
#-----------------------------------------------------------
|
||||||
|
# Vivado v2023.2 (64-bit)
|
||||||
|
# SW Build 4029153 on Fri Oct 13 20:14:34 MDT 2023
|
||||||
|
# IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
|
||||||
|
# SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
|
||||||
|
# Start of session at: Tue Jul 9 23:43:44 2024
|
||||||
|
# Process ID: 8060
|
||||||
|
# Current directory: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1
|
||||||
|
# Command line: vivado.exe -log phase_locked_loop.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source phase_locked_loop.tcl
|
||||||
|
# Log file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1/phase_locked_loop.vds
|
||||||
|
# Journal file: D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.runs/phase_locked_loop_synth_1\vivado.jou
|
||||||
|
# Running On: Viviana, OS: Windows, CPU Frequency: 2995 MHz, CPU Physical cores: 14, Host memory: 34070 MB
|
||||||
|
#-----------------------------------------------------------
|
||||||
|
source phase_locked_loop.tcl -notrace
|
||||||
BIN
PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.pb
Normal file
BIN
PipelineProcessor.runs/phase_locked_loop_synth_1/vivado.pb
Normal file
Binary file not shown.
@@ -0,0 +1,670 @@
|
|||||||
|
{
|
||||||
|
"schema": "xilinx.com:schema:json_instance:1.0",
|
||||||
|
"ip_inst": {
|
||||||
|
"xci_name": "phase_locked_loop",
|
||||||
|
"component_reference": "xilinx.com:ip:clk_wiz:6.0",
|
||||||
|
"ip_revision": "13",
|
||||||
|
"gen_directory": "../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop",
|
||||||
|
"parameters": {
|
||||||
|
"component_parameters": {
|
||||||
|
"Component_Name": [ { "value": "phase_locked_loop", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PRIMITIVE": [ { "value": "PLL", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "10.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT1_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT2_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT3_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT4_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT5_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT6_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKOUT7_DRIVES": [ { "value": "BUFG", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_LOCKED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"RESET_PORT": [ { "value": "reset", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MMCM_DIVCLK_DIVIDE": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MMCM_CLKFBOUT_MULT_F": [ { "value": "41", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_COMPENSATION": [ { "value": "ZHOLD", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT0_DIVIDE_F": [ { "value": "82", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"RESET_TYPE": [ { "value": "ACTIVE_HIGH", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
|
||||||
|
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_JITTER": [ { "value": "446.763", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT1_PHASE_ERROR": [ { "value": "313.282", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
|
||||||
|
"INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
|
||||||
|
"AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
|
||||||
|
"PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"model_parameters": {
|
||||||
|
"C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"c_component_name": [ { "value": "phase_locked_loop", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_RESET_LOW": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_LOCKED": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INCLK_SUM_ROW1": [ { "value": "__primary_________100.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__10.00000______0.000______50.0______446.763____313.282", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_OUT_FREQ": [ { "value": "10.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKFBOUT_MULT_F": [ { "value": "41.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
|
||||||
|
"C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_DIVCLK_DIVIDE": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "82.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_RESET_PORT": [ { "value": "reset", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_PRIMITIVE": [ { "value": "PLL", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
|
||||||
|
"C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE2_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE3_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE4_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE5_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE6_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_DIVIDE7_AUTO": [ { "value": "0.012195121951219513", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT0_ACTUAL_FREQ": [ { "value": "10.00000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
|
||||||
|
"C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_D_MAX": [ { "value": "42.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_VCO_MIN": [ { "value": "800.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
|
||||||
|
"C_VCO_MAX": [ { "value": "1600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
|
||||||
|
},
|
||||||
|
"project_parameters": {
|
||||||
|
"ARCHITECTURE": [ { "value": "artix7" } ],
|
||||||
|
"BASE_BOARD_PART": [ { "value": "" } ],
|
||||||
|
"BOARD_CONNECTIONS": [ { "value": "" } ],
|
||||||
|
"DEVICE": [ { "value": "xc7a35t" } ],
|
||||||
|
"PACKAGE": [ { "value": "fgg484" } ],
|
||||||
|
"PREFHDL": [ { "value": "VERILOG" } ],
|
||||||
|
"SILICON_REVISION": [ { "value": "" } ],
|
||||||
|
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
|
||||||
|
"SPEEDGRADE": [ { "value": "-1" } ],
|
||||||
|
"STATIC_POWER": [ { "value": "" } ],
|
||||||
|
"TEMPERATURE_GRADE": [ { "value": "" } ]
|
||||||
|
},
|
||||||
|
"runtime_parameters": {
|
||||||
|
"IPCONTEXT": [ { "value": "IP_Flow" } ],
|
||||||
|
"IPREVISION": [ { "value": "13" } ],
|
||||||
|
"MANAGED": [ { "value": "TRUE" } ],
|
||||||
|
"OUTPUTDIR": [ { "value": "../../../../PipelineProcessor.gen/sources_1/ip/phase_locked_loop" } ],
|
||||||
|
"SELECTEDSIMMODEL": [ { "value": "" } ],
|
||||||
|
"SHAREDDIR": [ { "value": "." } ],
|
||||||
|
"SWVERSION": [ { "value": "2023.2" } ],
|
||||||
|
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"boundary": {
|
||||||
|
"ports": {
|
||||||
|
"reset": [ { "direction": "in", "driver_value": "0" } ],
|
||||||
|
"clk_in1": [ { "direction": "in" } ],
|
||||||
|
"clk_out1": [ { "direction": "out" } ],
|
||||||
|
"locked": [ { "direction": "out" } ]
|
||||||
|
},
|
||||||
|
"interfaces": {
|
||||||
|
"reset": {
|
||||||
|
"vlnv": "xilinx.com:signal:reset:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"RST": [ { "physical_name": "reset" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"clock_CLK_IN1": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "slave",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK_IN1": [ { "physical_name": "clk_in1" } ]
|
||||||
|
}
|
||||||
|
},
|
||||||
|
"clock_CLK_OUT1": {
|
||||||
|
"vlnv": "xilinx.com:signal:clock:1.0",
|
||||||
|
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
|
||||||
|
"mode": "master",
|
||||||
|
"parameters": {
|
||||||
|
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
|
||||||
|
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
|
||||||
|
},
|
||||||
|
"port_maps": {
|
||||||
|
"CLK_OUT1": [ { "physical_name": "clk_out1" } ]
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
37
PipelineProcessor.srcs/sources_1/new/ALU.v
Normal file
37
PipelineProcessor.srcs/sources_1/new/ALU.v
Normal file
@@ -0,0 +1,37 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
module ALU (
|
||||||
|
input [ 4:0] funct,
|
||||||
|
input [31:0] in_1,
|
||||||
|
input [31:0] in_2,
|
||||||
|
output [31:0] result
|
||||||
|
);
|
||||||
|
|
||||||
|
wire lt_signed;
|
||||||
|
|
||||||
|
assign lt_signed = (in_1[31] ^ in_2[31]) ? ((in_1[31] == 1'b0 && in_2[31] == 1'b1) ? 0 : 1):
|
||||||
|
(in_1[30:0] < in_2[30:0]);
|
||||||
|
|
||||||
|
always @(*) begin
|
||||||
|
case (funct)
|
||||||
|
5'b00000: result = in_1 & in_2; // 0, and
|
||||||
|
5'b00001: result = in_1 | in_2; // 1, or
|
||||||
|
5'b00010: result = in_1 + in_2; // 2, add
|
||||||
|
5'b00110: result = in_1 - in_2; // 6, sub
|
||||||
|
5'b00111: result = {31'b0, lt_signed}; // 7, slt signed
|
||||||
|
5'b01000: result = {31'b0, in_1 < in_2}; // 8, slt unsigned
|
||||||
|
5'b01100: result = ~(in_1 | in_2); // 12, nor
|
||||||
|
5'b01101: result = in_1 ^ in_2; // 13, xor
|
||||||
|
5'b10000: result = in_2 << in_1[4:0]; // 16, sll
|
||||||
|
5'b10001: result = {31'b0, in_1 == in_2}; // 17, eq
|
||||||
|
5'b10010: result = {31'b0, ~(in_1 == in_2)}; // 18, neq
|
||||||
|
5'b10011: result = {31'b0, (in_1[31] == 1'b0 && in_1 != 32'h00000000)}; // 19, gtz
|
||||||
|
5'b10100: result = {31'b0, in_1[31] == 1'b1}; // 20, ltz
|
||||||
|
5'b10101: result = {31'b0, (in_1[31] == 1'b1 || in_1 == 32'h00000000)}; // 21, lez
|
||||||
|
5'b11000: result = {in2 >> in1[4:0]}; // 24, srl
|
||||||
|
5'b11001: result = {{32{in2[31]}}, in2} >> in1[4:0]; // 25, sra
|
||||||
|
5'b11010: result = in1 * in2; // 26, mul
|
||||||
|
default: result = 31'h00000000;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
236
PipelineProcessor.srcs/sources_1/new/CPU.v
Normal file
236
PipelineProcessor.srcs/sources_1/new/CPU.v
Normal file
@@ -0,0 +1,236 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module CPU (
|
||||||
|
input hardware_clk,
|
||||||
|
input reset,
|
||||||
|
output [11:0] bcd_control
|
||||||
|
);
|
||||||
|
|
||||||
|
// first, we split the clock
|
||||||
|
wire clk;
|
||||||
|
phase_locked_loop pll (
|
||||||
|
.clk_in1 (hardware_clk),
|
||||||
|
.clk_out1(clk)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Out of IF
|
||||||
|
wire IF_fetched_instruction;
|
||||||
|
wire IF_PC_plus_4;
|
||||||
|
|
||||||
|
// Out of ID
|
||||||
|
wire [1:0] ID_PC_jump;
|
||||||
|
wire [31:0] ID_branch_target;
|
||||||
|
wire [31:0] ID_jump_target;
|
||||||
|
wire [31:0] ID_jump_register_target;
|
||||||
|
wire ID_is_branch;
|
||||||
|
wire ID_is_loadword;
|
||||||
|
wire ID_register_write;
|
||||||
|
wire ID_WB_source;
|
||||||
|
wire ID_memory_write;
|
||||||
|
wire [4:0] ID_ALU_funtion;
|
||||||
|
wire ID_ALU_source1;
|
||||||
|
wire ID_ALU_source2;
|
||||||
|
wire ID_register_write_desination_source;
|
||||||
|
wire [31:0] ID_PC_plus_4;
|
||||||
|
wire [31:0] ID_register_file_read_A;
|
||||||
|
wire [31:0] ID_register_file_read_B;
|
||||||
|
wire [4:0] ID_shamt;
|
||||||
|
wire [31:0] ID_extended_immediate;
|
||||||
|
wire [4:0] ID_rs_address;
|
||||||
|
wire [4:0] ID_rt_address;
|
||||||
|
wire [4:0] ID_rd_address;
|
||||||
|
|
||||||
|
// Out of EX
|
||||||
|
wire EX_PC_branch;
|
||||||
|
wire [31:0] EX_branch_target;
|
||||||
|
wire EX_register_write;
|
||||||
|
wire EX_WB_source;
|
||||||
|
wire EX_memory_write;
|
||||||
|
wire [31:0] EX_ALU_result;
|
||||||
|
wire [31:0] EX_memory_write_data;
|
||||||
|
wire [4:0] EX_register_write_destination;
|
||||||
|
wire [4:0] EX_rs_address;
|
||||||
|
wire [4:0] EX_rt_address;
|
||||||
|
|
||||||
|
// Out of MEM
|
||||||
|
wire [4:0] MEM_rt_address;
|
||||||
|
wire MEM_register_write;
|
||||||
|
wire MEM_WB_source;
|
||||||
|
wire [31:0] MEM_memory_read_data;
|
||||||
|
wire [31:0] MEM_ALU_result;
|
||||||
|
wire [4:0] MEM_register_write_destination;
|
||||||
|
wire MEM_data_memory_write;
|
||||||
|
wire [31:0] MEM_data_memory_address;
|
||||||
|
wire [31:0] MEM_data_memory_write_data;
|
||||||
|
|
||||||
|
// Out of WB
|
||||||
|
wire WB_register_write;
|
||||||
|
wire [31:0] WB_register_write_data;
|
||||||
|
wire [4:0] WB_register_write_address;
|
||||||
|
|
||||||
|
// Out of hazard control
|
||||||
|
wire [1:0] hazard_IFID_source;
|
||||||
|
wire hazard_IDEX_source;
|
||||||
|
wire hazard_IF_need_stall;
|
||||||
|
|
||||||
|
// Out of EXforward
|
||||||
|
wire [1:0] EXforward_IDA_source;
|
||||||
|
wire [1:0] EXforward_IDB_source;
|
||||||
|
|
||||||
|
// Out of mem forward
|
||||||
|
wire MEMforward_MEM_write_data_source;
|
||||||
|
|
||||||
|
// Out of data memory
|
||||||
|
wire [31:0] datamemory_read_data;
|
||||||
|
wire [31:0] bcd_hardwire_control;
|
||||||
|
|
||||||
|
assign bcd_control = bcd_hardwire_control[11:0];
|
||||||
|
|
||||||
|
InstFetch instruction_fetch (
|
||||||
|
.clk(clk),
|
||||||
|
.branch_target(EX_branch_target),
|
||||||
|
.jump_target(ID_jump_target),
|
||||||
|
.jump_register_target(ID_jump_register_target),
|
||||||
|
.PC_jump(ID_PC_jump),
|
||||||
|
.PC_branch(EX_PC_branch),
|
||||||
|
.need_stall(hazard_IF_need_stall),
|
||||||
|
.fetched_instruction(IF_fetched_instruction),
|
||||||
|
.PC_plus_4(IF_PC_plus_4),
|
||||||
|
);
|
||||||
|
|
||||||
|
InstDecode instruction_decode (
|
||||||
|
.clk(clk),
|
||||||
|
.prev_fetched_instruction(IF_fetched_instruction),
|
||||||
|
.prev_PC_plus_4(IF_PC_plus_4),
|
||||||
|
.IFIDSrc(hazard_IFID_source),
|
||||||
|
.WB_write_enable(WB_write_enable),
|
||||||
|
.WB_write_address(WB_write_address),
|
||||||
|
.WB_write_data(WB_write_data),
|
||||||
|
.PC_jump(ID_PC_jump),
|
||||||
|
.jump_target(ID_jump_target),
|
||||||
|
.jump_register_target(ID_jump_register_target),
|
||||||
|
.is_loadword(ID_is_loadword),
|
||||||
|
.is_branch(ID_is_branch),
|
||||||
|
.WB_source(ID_WB_source),
|
||||||
|
.memory_write(ID_memory_write),
|
||||||
|
.ALU_function(ID_ALU_funtion),
|
||||||
|
.ALU_source1(ID_ALU_source1),
|
||||||
|
.ALU_source2(ID_ALU_source2),
|
||||||
|
.register_write_destination_source(ID_register_write_desination_source),
|
||||||
|
.register_write(ID_register_write),
|
||||||
|
.PC_plus_4(ID_PC_plus_4),
|
||||||
|
.register_file_read_A(ID_register_file_read_A),
|
||||||
|
.register_file_read_B(ID_register_file_read_B),
|
||||||
|
.shamt(ID_shamt),
|
||||||
|
.extended_immediate(ID_extended_immediate),
|
||||||
|
.rs_address(ID_rs_address),
|
||||||
|
.rt_address(ID_rt_address),
|
||||||
|
.rd_address(ID_rd_address)
|
||||||
|
);
|
||||||
|
|
||||||
|
Execution execution (
|
||||||
|
.clk(clk),
|
||||||
|
.prev_is_branch(ID_is_branch),
|
||||||
|
.prev_WB_source(ID_WB_source),
|
||||||
|
.prev_memory_write(ID_memory_write),
|
||||||
|
.prev_ALU_function(ID_ALU_funtion),
|
||||||
|
.prev_ALU_source1(ID_ALU_source1),
|
||||||
|
.prev_ALU_source2(ID_ALU_source2),
|
||||||
|
.prev_register_write_destination_source(ID_register_write_desination_source),
|
||||||
|
.prev_register_write(ID_register_write),
|
||||||
|
.prev_PC_plus_4(ID_PC_plus_4),
|
||||||
|
.prev_register_file_read_A(ID_register_file_read_A),
|
||||||
|
.prev_register_file_read_B(ID_register_file_read_B),
|
||||||
|
.prev_shamt(ID_shamt),
|
||||||
|
.prev_extended_immediate(ID_extended_immediate),
|
||||||
|
.prev_rs_address(ID_rs_address),
|
||||||
|
.prev_rt_address(ID_rt_address),
|
||||||
|
.prev_rd_address(ID_rd_address),
|
||||||
|
.IDEXSrc(hazard_IDEX_source),
|
||||||
|
.operandASrc(EXforward_IDA_source),
|
||||||
|
.operandBSrc(EXforward_IDB_source),
|
||||||
|
.MEM_forwarded_data(MEM_ALU_result),
|
||||||
|
.WB_forwarded_data(WB_register_write_data),
|
||||||
|
.PC_branch(EX_PC_branch),
|
||||||
|
.branch_target(EX_branch_target),
|
||||||
|
.register_write(EX_register_write),
|
||||||
|
.WB_source(EX_WB_source),
|
||||||
|
.memory_write(EX_memory_write),
|
||||||
|
.ALU_result(EX_ALU_result),
|
||||||
|
.memory_write_data(EX_memory_write_data),
|
||||||
|
.register_write_destination(EX_register_write_destination),
|
||||||
|
.rs_address(EX_rs_address),
|
||||||
|
.rt_address(EX_rt_address)
|
||||||
|
);
|
||||||
|
|
||||||
|
MemoryAccess memory_access (
|
||||||
|
.clk(clk),
|
||||||
|
.prev_register_write(EX_register_write),
|
||||||
|
.prev_WB_source(EX_WB_source),
|
||||||
|
.prev_memory_write(EX_memory_write),
|
||||||
|
.prev_ALU_result(EX_ALU_result),
|
||||||
|
.prev_memory_write_data(EX_memory_write_data),
|
||||||
|
.prev_register_write_destination(EX_register_write_destination),
|
||||||
|
.prev_rt_address(EX_rt_address),
|
||||||
|
.MEM_write_data_source(MEMforward_MEM_write_data_source),
|
||||||
|
.WB_forwarded_data(WB_register_write_data),
|
||||||
|
.rt_address(MEM_rt_address),
|
||||||
|
.register_write(MEM_register_write),
|
||||||
|
.WB_source(MEM_WB_source),
|
||||||
|
.memory_read_data(MEM_memory_read_data),
|
||||||
|
.ALU_result(MEM_ALU_result),
|
||||||
|
.register_write_destination(MEM_register_write_destination),
|
||||||
|
|
||||||
|
.data_memory_write(MEM_data_memory_write),
|
||||||
|
.data_memory_address(MEM_data_memory_address),
|
||||||
|
.data_memory_write_data(MEM_data_memory_write_data),
|
||||||
|
.data_memory_read_data(datamemory_read_data)
|
||||||
|
);
|
||||||
|
|
||||||
|
WriteBack write_back (
|
||||||
|
.clk(clk),
|
||||||
|
.prev_register_write(MEM_register_write),
|
||||||
|
.prev_WB_source(MEM_WB_source),
|
||||||
|
.prev_memory_read_data(MEM_memory_read_data),
|
||||||
|
.prev_ALU_result(MEM_ALU_result),
|
||||||
|
.prev_register_write_destination(MEM_register_write_destination),
|
||||||
|
.register_write(WB_register_write),
|
||||||
|
.register_write_data(WB_register_write_data),
|
||||||
|
.register_write_addr(WB_register_write_address),
|
||||||
|
);
|
||||||
|
|
||||||
|
DataMemory data_memory (
|
||||||
|
.clk(clk),
|
||||||
|
.address(MEM_data_memory_address),
|
||||||
|
.write_enable(MEM_data_memory_write),
|
||||||
|
.write_data(MEM_data_memory_write_data),
|
||||||
|
.read_data(datamemory_read_data),
|
||||||
|
.bcd_hardwire(bcd_hardwire_control)
|
||||||
|
);
|
||||||
|
|
||||||
|
ExecutionForward execution_forward (
|
||||||
|
.EX_rs_address(EX_rs_address),
|
||||||
|
.EX_rt_address(EX_rt_address),
|
||||||
|
.MEM_register_write(MEM_register_write),
|
||||||
|
.MEM_register_write_address(MEM_register_write_address),
|
||||||
|
.WB_register_write(WB_register_write),
|
||||||
|
.WB_register_write_address(WB_register_write_address),
|
||||||
|
.IDA_source(EXforward_IDA_source),
|
||||||
|
.IDB_source(EXforward_IDB_source)
|
||||||
|
);
|
||||||
|
|
||||||
|
MemoryForward memory_forward (
|
||||||
|
.WB_register_write(WB_register_write),
|
||||||
|
.WB_register_write_address(WB_register_write_address),
|
||||||
|
.MEM_rt_address(MEM_rt_address),
|
||||||
|
.MEM_write_data_source(MEMforward_MEM_write_data_source),
|
||||||
|
);
|
||||||
|
|
||||||
|
HazardUnit hazard_unit (
|
||||||
|
.PC_jump(ID_PC_jump),
|
||||||
|
.is_loadword(ID_is_loadword),
|
||||||
|
.PC_branch(EX_PC_branch),
|
||||||
|
.IFID_source(hazard_IFID_source),
|
||||||
|
.IDEX_source(hazard_IDEX_source),
|
||||||
|
.IF_need_stall(hazard_IF_need_stall)
|
||||||
|
);
|
||||||
|
endmodule
|
||||||
76
PipelineProcessor.srcs/sources_1/new/ControlUnit.v
Normal file
76
PipelineProcessor.srcs/sources_1/new/ControlUnit.v
Normal file
@@ -0,0 +1,76 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
module ControlUnit (
|
||||||
|
input [5:0] opcode,
|
||||||
|
input [5:0] funct,
|
||||||
|
output [1:0] PC_jump,
|
||||||
|
output is_branch,
|
||||||
|
output is_loadword,
|
||||||
|
output write_ra,
|
||||||
|
output ra_addr_source,
|
||||||
|
output WB_source,
|
||||||
|
output memory_write,
|
||||||
|
output [4:0] ALU_function,
|
||||||
|
output ALU_source1,
|
||||||
|
output ALU_source2,
|
||||||
|
output register_write,
|
||||||
|
output register_write_destination_source,
|
||||||
|
output [1:0] extendop
|
||||||
|
);
|
||||||
|
|
||||||
|
assign PC_jump = (opcode == 6'h2 || opcode == 6'h3) ? 2'b01:
|
||||||
|
(opcode == 6'h0 && (funct == 6'h8 || funct == 6'h9)) ? 2'b10 : 2'b00;
|
||||||
|
|
||||||
|
assign is_branch = (opcode == 6'h4 || opcode == 6'h5 || opcode == 6'h6 ||
|
||||||
|
opcode == 6'h7 || opcode == 6'h1) ? 1 : 0;
|
||||||
|
|
||||||
|
assign is_loadword = (opcode == 6'h23) ? 1 : 0;
|
||||||
|
|
||||||
|
assign write_ra = (opcode == 6'h3) ? 1 : (opcode == 6'h0 && funct == 6'h9) ? 1 : 0;
|
||||||
|
|
||||||
|
assign ra_addr_source = (opcode == 6'h0 && funct == 6'h9) ? 1 : 0;
|
||||||
|
|
||||||
|
assign register_write = (opcode == 6'h2b || opcode == 6'h4 || opcode == 6'h5 ||
|
||||||
|
opcode == 6'h6 || opcode == 6'h7 || opcode == 6'h1 ||
|
||||||
|
opcode == 6'h1 || opcode == 6'h2 || opcode == 6'h3 ||
|
||||||
|
(opcode == 6'h0 && (funct == 6'h8 || funct == 6'h9))) ? 0 : 1;
|
||||||
|
|
||||||
|
assign WB_source = (opcode == 6'h23) ? 1 : 0;
|
||||||
|
|
||||||
|
assign memory_write = (opcode == 6'h2b) ? 1 : 0;
|
||||||
|
|
||||||
|
assign ALU_function = (opcode == 6'h0 && funct == 6'h24) ? 5'b00000:
|
||||||
|
(opcode == 6'h0 && funct == 6'h25) ? 5'b00001:
|
||||||
|
(opcode == 6'h0 && (funct == 6'h22 || funct == 6'h23)) ? 5'b00110:
|
||||||
|
(opcode == 6'ha || (opcode == 6'h0 && funct == 6'h2a)) ? 5'b00111:
|
||||||
|
(opcode == 6'hb || (opcode == 6'h0 && funct == 56'h2b)) ? 5'b01000:
|
||||||
|
(opcode == 6'h0 && funct == 6'h27) ? 5'b01100:
|
||||||
|
(opcode == 6'h0 && funct == 6'h26) ? 5'b01101:
|
||||||
|
(opcode == 6'h0 && funct == 6'h0) ? 5'b10000:
|
||||||
|
(opcode == 6'h4) ? 5'b10001:
|
||||||
|
(opcode == 6'h5) ? 5'b10010:
|
||||||
|
(opcode == 6'h7) ? 5'b10011:
|
||||||
|
(opcode == 6'h1) ? 5'b10100:
|
||||||
|
(opcode == 6'h6) ? 5'b10101:
|
||||||
|
(opcode == 6'h0 && funct == 6'h2) ? 5'b11000:
|
||||||
|
(opcode == 6'h0 && funct == 6'h3) ? 5'b11001:
|
||||||
|
(opcode == 6'h0 && funct == 6'h18) ? 5'b11010:
|
||||||
|
5'b00010;
|
||||||
|
|
||||||
|
assign ALU_source1 = (opcode == 6'h0 &&
|
||||||
|
(funct == 6'h0 || funct == 6'h2 || funct == 6'h3)) ? 1 : 0;
|
||||||
|
|
||||||
|
assign ALU_source2 = (opcode == 6'h23 || opcode == 6'h2b || opcode == 6'hf ||
|
||||||
|
opcode == 6'h8 || opcode == 6'h9 || opcode == 6'hc || opcode == 6'ha ||
|
||||||
|
opcode == 6'hb) ? 1 : 0;
|
||||||
|
|
||||||
|
assign register_write_destination_source = (opcode == 6'h23 || opcode == 6'h8 ||
|
||||||
|
opcode == 6'h9 || opcode == 6'hc ||
|
||||||
|
opcode == 6'ha || opcode == 6'hb ||
|
||||||
|
(opcode == 6'h0 &&
|
||||||
|
(funct == 6'h0 || funct == 6'h2 ||
|
||||||
|
funct == 6'h3))) ? 0 : 1;
|
||||||
|
|
||||||
|
assign extendop = (opcode == 6'hf) ? 2'b10:
|
||||||
|
(opcode == 6'hc) ? 2'b01:2'b00;
|
||||||
|
endmodule
|
||||||
24
PipelineProcessor.srcs/sources_1/new/DataMemory.v
Normal file
24
PipelineProcessor.srcs/sources_1/new/DataMemory.v
Normal file
@@ -0,0 +1,24 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
module DataMemory (
|
||||||
|
input clk,
|
||||||
|
input [31:0] address,
|
||||||
|
input write_enable,
|
||||||
|
input [31:0] write_data,
|
||||||
|
output reg [31:0] read_data,
|
||||||
|
output [31:0] bcd_hardwire
|
||||||
|
);
|
||||||
|
parameter integer MEM_SIZE = 1024;
|
||||||
|
parameter integer START_ADDRESS = 32'h00000000;
|
||||||
|
|
||||||
|
reg [31:0] memory_data[MEM_SIZE + START_ADDRESS - 1:START_ADDRESS];
|
||||||
|
|
||||||
|
assign bcd_hardwire = memory_data[START_ADDRESS + 4];
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (write_enable) begin
|
||||||
|
memory_data[address] <= write_data;
|
||||||
|
end
|
||||||
|
read_data <= memory_data[address];
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
135
PipelineProcessor.srcs/sources_1/new/Execution.v
Normal file
135
PipelineProcessor.srcs/sources_1/new/Execution.v
Normal file
@@ -0,0 +1,135 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module Execution (
|
||||||
|
input clk,
|
||||||
|
// From prev stage
|
||||||
|
input prev_is_branch,
|
||||||
|
input prev_WB_source,
|
||||||
|
input prev_memory_write,
|
||||||
|
input [4:0] prev_ALU_function,
|
||||||
|
input prev_ALU_source1,
|
||||||
|
input prev_ALU_source2,
|
||||||
|
input prev_register_write_destination_source,
|
||||||
|
input prev_register_write,
|
||||||
|
input [31:0] prev_PC_plus_4,
|
||||||
|
input [31:0] prev_register_file_read_A,
|
||||||
|
input [31:0] prev_register_file_read_B,
|
||||||
|
input [4:0] prev_shamt,
|
||||||
|
input [31:0] prev_extended_immediate,
|
||||||
|
input [4:0] prev_rs_address,
|
||||||
|
input [4:0] prev_rt_address,
|
||||||
|
input [4:0] prev_rd_address,
|
||||||
|
// From hazard unit
|
||||||
|
input IDEXSrc,
|
||||||
|
// From forward unit
|
||||||
|
input [1:0] operandASrc,
|
||||||
|
input [1:0] operandBSrc,
|
||||||
|
// From MEM
|
||||||
|
input [31:0] MEM_forwarded_data,
|
||||||
|
// From WB
|
||||||
|
input [31:0] WB_forwarded_data,
|
||||||
|
// To IF stage, also hazard unit
|
||||||
|
output PC_branch,
|
||||||
|
// Only to IF stage
|
||||||
|
output [31:0] branch_target,
|
||||||
|
// To next stage
|
||||||
|
output register_write,
|
||||||
|
output WB_source,
|
||||||
|
output memory_write,
|
||||||
|
output [31:0] ALU_result,
|
||||||
|
output [31:0] memory_write_data,
|
||||||
|
output [4:0] register_write_destination,
|
||||||
|
// To forward unit
|
||||||
|
output [4:0] rs_address,
|
||||||
|
output [4:0] rt_address
|
||||||
|
);
|
||||||
|
|
||||||
|
reg EX_register_write;
|
||||||
|
reg EX_WB_source;
|
||||||
|
reg EX_memory_write;
|
||||||
|
reg EX_is_branch;
|
||||||
|
reg [4:0] EX_ALU_function;
|
||||||
|
reg EX_ALU_source1;
|
||||||
|
reg EX_ALU_source2;
|
||||||
|
reg EX_register_write_destination_source;
|
||||||
|
reg [31:0] EX_PC_plus_4;
|
||||||
|
reg [31:0] EX_register_read_A;
|
||||||
|
reg [31:0] EX_register_read_B;
|
||||||
|
reg [4:0] EX_shamt;
|
||||||
|
reg [31:0] EX_extended_immediate;
|
||||||
|
reg [4:0] EX_rs_address;
|
||||||
|
reg [4:0] EX_rt_address;
|
||||||
|
reg [4:0] EX_rd_address;
|
||||||
|
|
||||||
|
// ALU Part
|
||||||
|
wire [31:0] ALU_in1;
|
||||||
|
wire [31:0] RF_read_B_include_forward;
|
||||||
|
wire [31:0] ALU_in2;
|
||||||
|
wire [31:0] ALU_out;
|
||||||
|
assign ALU_in1 = (EX_ALU_source1 == 1'b1) ? EX_shamt :
|
||||||
|
(operandASrc == 2'b00) ? EX_register_read_A :
|
||||||
|
(operandASrc == 2'b01) ? MEM_forwarded_data :
|
||||||
|
(operandASrc == 2'b10) ? WB_forwarded_data : 32'h00000000;
|
||||||
|
|
||||||
|
assign RF_read_B_include_forward = (operandBSrc == 2'b00) ? EX_register_read_B :
|
||||||
|
(operandBSrc == 2'b01) ? MEM_forwarded_data :
|
||||||
|
(operandBSrc == 2'b10) ? WB_forwarded_data : 32'h00000000;
|
||||||
|
assign ALU_in2 = (EX_ALU_source2 == 1'b1) ? EX_extended_immediate : RF_read_B_include_forward;
|
||||||
|
|
||||||
|
ALU alu(
|
||||||
|
.funct(EX_ALU_function),
|
||||||
|
.in_1(ALU_in1),
|
||||||
|
.in_2(ALU_in2),
|
||||||
|
.result(ALU_out)
|
||||||
|
);
|
||||||
|
|
||||||
|
// All output signals
|
||||||
|
assign PC_branch = EX_is_branch & ALU_out[0];
|
||||||
|
assign branch_target = EX_PC_plus_4 + (EX_extended_immediate << 2);
|
||||||
|
assign register_write = EX_register_write;
|
||||||
|
assign WB_source = EX_WB_source;
|
||||||
|
assign memory_write = EX_memory_write;
|
||||||
|
assign ALU_result = ALU_out;
|
||||||
|
assign memory_write_data = RF_read_B_include_forward;
|
||||||
|
assign register_write_destination = (EX_register_write_destination_source == 1'b0) ?
|
||||||
|
EX_rt_address : EX_rd_address;
|
||||||
|
assign rs_address = EX_rs_address;
|
||||||
|
assign rt_address = EX_rt_address;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (IDEXSrc == 1'b1) begin
|
||||||
|
EX_register_write <= 1'b0;
|
||||||
|
EX_WB_source <= 1'b0;
|
||||||
|
EX_memory_write <= 1'b0;
|
||||||
|
EX_is_branch <= 1'b0;
|
||||||
|
EX_ALU_function <= 5'b00000;
|
||||||
|
EX_ALU_source1 <= 1'b0;
|
||||||
|
EX_ALU_source2 <= 1'b0;
|
||||||
|
EX_register_write_destination_source <= 1'b0;
|
||||||
|
EX_PC_plus_4 <= 32'h00000000;
|
||||||
|
EX_register_read_A <= 32'h00000000;
|
||||||
|
EX_register_read_B <= 32'h00000000;
|
||||||
|
EX_shamt <= 5'b00000;
|
||||||
|
EX_extended_immediate <= 32'h00000000;
|
||||||
|
EX_rs_address <= 5'b00000;
|
||||||
|
EX_rt_address <= 5'b00000;
|
||||||
|
EX_rd_address <= 5'b00000;
|
||||||
|
end else begin
|
||||||
|
EX_register_write <= prev_register_write;
|
||||||
|
EX_WB_source <= prev_WB_source;
|
||||||
|
EX_memory_write <= prev_memory_write;
|
||||||
|
EX_is_branch <= prev_is_branch;
|
||||||
|
EX_ALU_function <= prev_ALU_function;
|
||||||
|
EX_ALU_source1 <= prev_ALU_source1;
|
||||||
|
EX_ALU_source2 <= prev_ALU_source2;
|
||||||
|
EX_register_write_destination_source <= prev_register_write_destination_source;
|
||||||
|
EX_PC_plus_4 <= prev_PC_plus_4;
|
||||||
|
EX_register_read_A <= prev_register_file_read_A;
|
||||||
|
EX_register_read_B <= prev_register_file_read_B;
|
||||||
|
EX_shamt <= prev_shamt;
|
||||||
|
EX_extended_immediate <= prev_extended_immediate;
|
||||||
|
EX_rs_address <= prev_rs_address;
|
||||||
|
EX_rt_address <= prev_rt_address;
|
||||||
|
EX_rd_address <= prev_rd_address;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
38
PipelineProcessor.srcs/sources_1/new/ExecutionForward.v
Normal file
38
PipelineProcessor.srcs/sources_1/new/ExecutionForward.v
Normal file
@@ -0,0 +1,38 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module ExecutionForward (
|
||||||
|
input [4:0] EX_rs_address,
|
||||||
|
input [4:0] EX_rt_address,
|
||||||
|
input MEM_register_write,
|
||||||
|
input [4:0] MEM_register_write_address,
|
||||||
|
input WB_register_write,
|
||||||
|
input [4:0] WB_register_write_address,
|
||||||
|
output [1:0] IDA_source,
|
||||||
|
output [1:0] IDB_source
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(*) begin
|
||||||
|
if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rs_address &&
|
||||||
|
EX_rs_address != 5'b00000) begin
|
||||||
|
IDA_source = 2'b00;
|
||||||
|
end else begin
|
||||||
|
if (WB_register_write == 1'b1 && WB_register_write_address == EX_rs_address &&
|
||||||
|
EX_rs_address != 5'b00000) begin
|
||||||
|
IDA_source = 2'b10;
|
||||||
|
end else begin
|
||||||
|
IDA_source = 2'b00;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
if (MEM_register_write == 1'b1 && MEM_register_write_address == EX_rt_address &&
|
||||||
|
EX_rt_address != 5'b00000) begin
|
||||||
|
IDB_source = 2'b00;
|
||||||
|
end else begin
|
||||||
|
if (WB_register_write == 1'b1 && WB_register_write_address == EX_rt_address &&
|
||||||
|
EX_rt_address != 5'b00000) begin
|
||||||
|
IDB_source = 2'b10;
|
||||||
|
end else begin
|
||||||
|
IDB_source = 2'b00;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
20
PipelineProcessor.srcs/sources_1/new/HazardUnit.v
Normal file
20
PipelineProcessor.srcs/sources_1/new/HazardUnit.v
Normal file
@@ -0,0 +1,20 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module HazardUnit (
|
||||||
|
input [1:0] PC_jump,
|
||||||
|
input is_loadword,
|
||||||
|
input PC_branch,
|
||||||
|
output [1:0] IFID_source,
|
||||||
|
output IDEX_source,
|
||||||
|
output IF_need_stall
|
||||||
|
);
|
||||||
|
|
||||||
|
wire is_jump;
|
||||||
|
assign is_jump = PC_jump == 2'b01 || PC_jump == 2'b10;
|
||||||
|
|
||||||
|
assign IFID_source = (is_loadword == 1'b1) ? 2'b10 :
|
||||||
|
(PC_branch == 1'b1 || is_jump == 1'b1) ? 2'b01 : 2'b00;
|
||||||
|
|
||||||
|
assign IDEX_source = (is_loadword == 1'b1 || PC_branch == 1'b1 || is_jump == 1'b1) ? 1 : 0;
|
||||||
|
|
||||||
|
assign IF_need_stall = (is_loadword == 1'b1) ? 1 : 0;
|
||||||
|
endmodule
|
||||||
11
PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v
Normal file
11
PipelineProcessor.srcs/sources_1/new/ImmediateExtender.v
Normal file
@@ -0,0 +1,11 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
module ImmediateExtender (
|
||||||
|
input [15:0] immediate,
|
||||||
|
input [ 1:0] extendop,
|
||||||
|
output [31:0] extended_immediate
|
||||||
|
);
|
||||||
|
|
||||||
|
assign extended_immediate = (extendop == 2'b00) ? {{16{immediate[15]}}, immediate}:
|
||||||
|
(extendop == 2'b01) ? {16'h0000, immediate}: {immediate, 16'h0000};
|
||||||
|
endmodule
|
||||||
138
PipelineProcessor.srcs/sources_1/new/InstDecode.v
Normal file
138
PipelineProcessor.srcs/sources_1/new/InstDecode.v
Normal file
@@ -0,0 +1,138 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module InstDecode (
|
||||||
|
input clk,
|
||||||
|
// From prev stage
|
||||||
|
input [31:0] prev_fetched_instruction,
|
||||||
|
input [31:0] prev_PC_plus_4,
|
||||||
|
// For hazard unit
|
||||||
|
input [1:0] IFIDSrc,
|
||||||
|
// From WB stage
|
||||||
|
input WB_write_enable,
|
||||||
|
input [4:0] WB_write_address,
|
||||||
|
input [31:0] WB_write_data,
|
||||||
|
// To IF stage
|
||||||
|
output [1:0] PC_jump,
|
||||||
|
output [31:0] jump_target,
|
||||||
|
output [31:0] jump_register_target,
|
||||||
|
// To hazard unit
|
||||||
|
output is_loadword,
|
||||||
|
// To next stage
|
||||||
|
output is_branch,
|
||||||
|
output WB_source,
|
||||||
|
output memory_write,
|
||||||
|
output [4:0] ALU_function,
|
||||||
|
output ALU_source1,
|
||||||
|
output ALU_source2,
|
||||||
|
output register_write_destination_source,
|
||||||
|
output register_write,
|
||||||
|
output [31:0] PC_plus_4,
|
||||||
|
output [31:0] register_file_read_A,
|
||||||
|
output [31:0] register_file_read_B,
|
||||||
|
output [4:0] shamt,
|
||||||
|
output [31:0] extended_immediate,
|
||||||
|
output [4:0] rs_address,
|
||||||
|
output [4:0] rt_address,
|
||||||
|
output [4:0] rd_address
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [31:0] IFID_instruction;
|
||||||
|
reg [31:0] IFID_PC_plus_4;
|
||||||
|
|
||||||
|
wire [ 5:0] opcode;
|
||||||
|
wire [ 4:0] rs;
|
||||||
|
wire [ 4:0] rt;
|
||||||
|
wire [ 4:0] rd;
|
||||||
|
wire [ 5:0] funct;
|
||||||
|
wire [25:0] j_addr;
|
||||||
|
wire [15:0] immediate;
|
||||||
|
|
||||||
|
// Signals derived from instruction
|
||||||
|
assign opcode = IFID_instruction[31:26];
|
||||||
|
assign rs = IFID_instruction[25:21];
|
||||||
|
assign rt = IFID_instruction[20:16];
|
||||||
|
assign rd = IFID_instruction[15:11];
|
||||||
|
assign shamt = IFID_instruction[10:6];
|
||||||
|
assign funct = IFID_instruction[5:0];
|
||||||
|
assign j_addr = IFID_instruction[25:0];
|
||||||
|
assign immediate = IFID_instruction[15:0];
|
||||||
|
|
||||||
|
// This output is directly derived from IFID regs
|
||||||
|
assign jump_target = {IFID_PC_plus_4[31:28], j_addr, 2'b00};
|
||||||
|
assign rs_address = rs;
|
||||||
|
assign rt_address = rt;
|
||||||
|
assign rd_address = rd;
|
||||||
|
|
||||||
|
// Signals to connect from control unit to register file and immediate extend unit
|
||||||
|
wire write_ra;
|
||||||
|
wire ra_addr_source;
|
||||||
|
wire extendop;
|
||||||
|
|
||||||
|
ControlUnit control_unit (
|
||||||
|
.opcode(opcode),
|
||||||
|
.funct(funct),
|
||||||
|
.PC_jump(PC_jump),
|
||||||
|
.is_branch(is_branch),
|
||||||
|
.is_loadword(is_loadword),
|
||||||
|
.write_ra(write_ra),
|
||||||
|
.ra_addr_source(ra_addr_source),
|
||||||
|
.WB_source(WB_source),
|
||||||
|
.memory_write(memory_write),
|
||||||
|
.ALU_function(ALU_function),
|
||||||
|
.ALU_source1(ALU_source1),
|
||||||
|
.ALU_source2(ALU_source2),
|
||||||
|
.register_write(register_write),
|
||||||
|
.register_write_destination_source(register_write_destination_source),
|
||||||
|
.extendop(extendop)
|
||||||
|
);
|
||||||
|
|
||||||
|
// Signal for register file
|
||||||
|
wire [31:0] RF_read_A_out;
|
||||||
|
wire [ 4:0] write_ra_addr_after_mux;
|
||||||
|
|
||||||
|
assign write_ra_addr_after_mux = (ra_addr_source == 1'b0) ? 5'b11111 : rd;
|
||||||
|
|
||||||
|
RegisterFile register_file (
|
||||||
|
.clk(clk),
|
||||||
|
.read_addr1(rs),
|
||||||
|
.read_addr2(rt),
|
||||||
|
.write_enable(WB_write_enable),
|
||||||
|
.write_addr(WB_write_address),
|
||||||
|
.write_data(WB_write_data),
|
||||||
|
.write_ra(write_ra),
|
||||||
|
.write_ra_addr(write_ra_addr_after_mux),
|
||||||
|
.write_ra_data(IFID_PC_plus_4),
|
||||||
|
.read_output1(RF_read_A_out),
|
||||||
|
.read_output2(register_file_read_B)
|
||||||
|
);
|
||||||
|
|
||||||
|
assign register_file_read_A = RF_read_A_out;
|
||||||
|
assign jump_register_target = RF_read_A_out;
|
||||||
|
|
||||||
|
ImmediateExtender immediate_extender(
|
||||||
|
.immediate(immediate),
|
||||||
|
.extendop(extendop),
|
||||||
|
.extended_immediate(extended_immediate)
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
case (IFIDSrc)
|
||||||
|
2'b00: begin
|
||||||
|
IFID_instruction <= prev_fetched_instruction;
|
||||||
|
IFID_PC_plus_4 <= prev_PC_plus_4;
|
||||||
|
end
|
||||||
|
2'b01: begin
|
||||||
|
IFID_instruction <= 32'h00000000;
|
||||||
|
IFID_PC_plus_4 <= 32'h00000000;
|
||||||
|
end
|
||||||
|
2'b10: begin
|
||||||
|
IFID_instruction <= IFID_instruction;
|
||||||
|
IFID_PC_plus_4 <= IFID_PC_plus_4;
|
||||||
|
end
|
||||||
|
default: begin
|
||||||
|
IFID_instruction <= 32'h00000000;
|
||||||
|
IFID_PC_plus_4 <= 32'h00000000;
|
||||||
|
end
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
39
PipelineProcessor.srcs/sources_1/new/InstFetch.v
Normal file
39
PipelineProcessor.srcs/sources_1/new/InstFetch.v
Normal file
@@ -0,0 +1,39 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module InstFetch (
|
||||||
|
input clk,
|
||||||
|
input [31:0] branch_target,
|
||||||
|
input [31:0] jump_target,
|
||||||
|
input [31:0] jump_register_target,
|
||||||
|
input [1:0] PC_jump,
|
||||||
|
input PC_branch,
|
||||||
|
input need_stall,
|
||||||
|
output [31:0] fetched_instruction,
|
||||||
|
output [31:0] PC_plus_4
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [31:0] PC;
|
||||||
|
InstructionMemory instruction_memory (
|
||||||
|
.address(PC),
|
||||||
|
.instruction(fetched_instruction)
|
||||||
|
);
|
||||||
|
|
||||||
|
wire adder_out;
|
||||||
|
assign adder_out = PC + 4;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (need_stall) begin
|
||||||
|
PC <= PC;
|
||||||
|
end else begin
|
||||||
|
if (PC_branch) begin
|
||||||
|
PC <= branch_target;
|
||||||
|
end else begin
|
||||||
|
case (PC_jump)
|
||||||
|
2'b00: PC <= adder_out;
|
||||||
|
2'b01: PC <= jump_target;
|
||||||
|
2'b10: PC <= jump_register_target;
|
||||||
|
default: PC <= adder_out;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
16
PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
Normal file
16
PipelineProcessor.srcs/sources_1/new/InstructionMemory.v
Normal file
@@ -0,0 +1,16 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
module InstructionMemory (
|
||||||
|
input [31:0] address,
|
||||||
|
output reg [31:0] instruction
|
||||||
|
);
|
||||||
|
|
||||||
|
always @(*) begin
|
||||||
|
case (address[31:2])
|
||||||
|
20'd0: instruction <= 32'h20210001;
|
||||||
|
20'd1: instruction <= 32'h08000000;
|
||||||
|
default: instruction <= 32'h00000000;
|
||||||
|
endcase
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
72
PipelineProcessor.srcs/sources_1/new/MemoryAccess.v
Normal file
72
PipelineProcessor.srcs/sources_1/new/MemoryAccess.v
Normal file
@@ -0,0 +1,72 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module MemoryAccess (
|
||||||
|
input clk,
|
||||||
|
// From prev stage
|
||||||
|
input prev_register_write,
|
||||||
|
input prev_WB_source,
|
||||||
|
input prev_memory_write,
|
||||||
|
input [31:0] prev_ALU_result,
|
||||||
|
input [31:0] prev_memory_write_data,
|
||||||
|
input [4:0] prev_register_write_destination,
|
||||||
|
input [4:0] prev_rt_address,
|
||||||
|
// From forward unit
|
||||||
|
input MEM_write_data_source,
|
||||||
|
// From WB
|
||||||
|
input [31:0] WB_forwarded_data,
|
||||||
|
// To Forward unit
|
||||||
|
output [4:0] rt_address,
|
||||||
|
// To next stage
|
||||||
|
output register_write,
|
||||||
|
output WB_source,
|
||||||
|
output [31:0] memory_read_data,
|
||||||
|
output [31:0] ALU_result,
|
||||||
|
output [4:0] register_write_destination,
|
||||||
|
|
||||||
|
// Data memory IO
|
||||||
|
output data_memory_write,
|
||||||
|
output [31:0] data_memory_address,
|
||||||
|
output [31:0] data_memory_write_data,
|
||||||
|
input [31:0] data_memory_read_data
|
||||||
|
);
|
||||||
|
|
||||||
|
reg MEM_register_write;
|
||||||
|
reg MEM_WB_source;
|
||||||
|
reg MEM_memory_write;
|
||||||
|
reg [31:0] MEM_ALU_result;
|
||||||
|
reg [31:0] MEM_memory_write_data;
|
||||||
|
reg [4:0] MEM_register_write_destination;
|
||||||
|
reg [4:0] MEM_rt_address;
|
||||||
|
|
||||||
|
// wire memory_write_data_include_forward;
|
||||||
|
// assign memory_write_data_include_forward = (MEM_write_data_source == 1'b0) ?
|
||||||
|
// MEM_memory_write_data : WB_forwarded_data;
|
||||||
|
|
||||||
|
// DataMemory data_memory(
|
||||||
|
// .clk(clk),
|
||||||
|
// .address(MEM_ALU_result),
|
||||||
|
// .write_enable(MEM_memory_write),
|
||||||
|
// .write_data(memory_write_data_include_forward),
|
||||||
|
// .read_data(memory_read_data)
|
||||||
|
// );
|
||||||
|
assign data_memory = MEM_memory_write;
|
||||||
|
assign data_memory_address = MEM_ALU_result;
|
||||||
|
assign data_memory_write_data = (MEM_write_data_source == 1'b0) ?
|
||||||
|
MEM_memory_write_data : WB_forwarded_data;
|
||||||
|
assign read_data = data_memory_read_data;
|
||||||
|
|
||||||
|
assign rt_address = MEM_rt_address;
|
||||||
|
assign register_write = MEM_register_write;
|
||||||
|
assign WB_source = MEM_WB_source;
|
||||||
|
assign ALU_result = MEM_ALU_result;
|
||||||
|
assign register_write_destination = MEM_register_write_destination;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
MEM_register_write <= prev_register_write;
|
||||||
|
MEM_WB_source <= prev_WB_source;
|
||||||
|
MEM_memory_write <= prev_memory_write;
|
||||||
|
MEM_ALU_result <= prev_ALU_result;
|
||||||
|
MEM_memory_write_data <= prev_memory_write_data;
|
||||||
|
MEM_register_write_destination <= prev_register_write_destination;
|
||||||
|
MEM_rt_address <= prev_rt_address;
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
11
PipelineProcessor.srcs/sources_1/new/MemoryForward.v
Normal file
11
PipelineProcessor.srcs/sources_1/new/MemoryForward.v
Normal file
@@ -0,0 +1,11 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module MemoryForward (
|
||||||
|
input WB_register_write,
|
||||||
|
input [4:0] WB_register_write_address,
|
||||||
|
input [4:0] MEM_rt_address,
|
||||||
|
output MEM_write_data_source
|
||||||
|
);
|
||||||
|
|
||||||
|
assign MEM_write_data_source = (WB_register_write == 1'b1) ?
|
||||||
|
((MEM_rt_address != 5'b00000 && WB_register_write_address == MEM_rt_address) ? 1 : 0) : 0;
|
||||||
|
endmodule
|
||||||
46
PipelineProcessor.srcs/sources_1/new/RegisterFile.v
Normal file
46
PipelineProcessor.srcs/sources_1/new/RegisterFile.v
Normal file
@@ -0,0 +1,46 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
|
||||||
|
module RegisterFile (
|
||||||
|
input clk,
|
||||||
|
input [4:0] read_addr1,
|
||||||
|
input [4:0] read_addr2,
|
||||||
|
input write_enable,
|
||||||
|
input [4:0] write_addr,
|
||||||
|
input [31:0] write_data,
|
||||||
|
input write_ra,
|
||||||
|
input [4:0] write_ra_addr,
|
||||||
|
input [31:0] write_ra_data,
|
||||||
|
output [31:0] read_output1,
|
||||||
|
output [31:0] read_output2
|
||||||
|
);
|
||||||
|
|
||||||
|
reg [31:0] registers[31:1];
|
||||||
|
|
||||||
|
assign read_output1 = (read_addr1 == 5'b00000) ? 32'h00000000 :
|
||||||
|
(read_addr1 == write_ra_addr) ? write_ra_data :
|
||||||
|
(read_addr1 == write_addr) ? write_data : registers[read_addr1];
|
||||||
|
|
||||||
|
assign read_output2 = (read_addr2 == 5'b00000) ? 32'h00000000 :
|
||||||
|
(read_addr2 == write_ra_addr) ? write_ra_data :
|
||||||
|
(read_addr2 == write_addr) ? write_data : registers[read_addr2];
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
if (write_addr == write_ra_addr) begin
|
||||||
|
if (write_ra) begin
|
||||||
|
registers[write_ra_addr] <= write_ra_data;
|
||||||
|
end else begin
|
||||||
|
if (write_enable) begin
|
||||||
|
registers[write_addr] <= write_data;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end else begin
|
||||||
|
if (write_ra) begin
|
||||||
|
registers[write_ra_addr] <= write_ra_data;
|
||||||
|
end
|
||||||
|
if (write_enable) begin
|
||||||
|
registers[write_addr] <= write_data;
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
33
PipelineProcessor.srcs/sources_1/new/WriteBack.v
Normal file
33
PipelineProcessor.srcs/sources_1/new/WriteBack.v
Normal file
@@ -0,0 +1,33 @@
|
|||||||
|
`timescale 1ns / 1ps
|
||||||
|
module WriteBack (
|
||||||
|
input clk,
|
||||||
|
// From prev stage
|
||||||
|
input prev_register_write,
|
||||||
|
input prev_WB_source,
|
||||||
|
input [31:0] prev_memory_read_data,
|
||||||
|
input [31:0] prev_ALU_result,
|
||||||
|
input [4:0] prev_register_write_destination,
|
||||||
|
// To many things, really
|
||||||
|
output register_write,
|
||||||
|
output [31:0] register_write_data,
|
||||||
|
output [4:0] register_write_addr
|
||||||
|
);
|
||||||
|
|
||||||
|
reg WB_register_write;
|
||||||
|
reg WB_WB_source;
|
||||||
|
reg [31:0] WB_memory_read_data;
|
||||||
|
reg [31:0] WB_ALU_result;
|
||||||
|
reg [4:0] WB_register_write_destination;
|
||||||
|
|
||||||
|
assign register_write = WB_register_write;
|
||||||
|
assign register_write_data = (WB_WB_source == 1'b0) ? WB_ALU_result : WB_memory_read_data;
|
||||||
|
assign register_write_addr = WB_register_write_destination;
|
||||||
|
|
||||||
|
always @(posedge clk) begin
|
||||||
|
WB_register_write <= prev_register_write;
|
||||||
|
WB_WB_source <= prev_WB_source;
|
||||||
|
WB_memory_read_data <= prev_memory_read_data;
|
||||||
|
WB_ALU_result <= prev_ALU_result;
|
||||||
|
WB_register_write_destination <= prev_register_write_destination;
|
||||||
|
end
|
||||||
|
endmodule
|
||||||
354
PipelineProcessor.xpr
Normal file
354
PipelineProcessor.xpr
Normal file
@@ -0,0 +1,354 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8"?>
|
||||||
|
<!-- Product Version: Vivado v2023.2 (64-bit) -->
|
||||||
|
<!-- -->
|
||||||
|
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||||
|
<!-- Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||||
|
|
||||||
|
<Project Product="Vivado" Version="7" Minor="65" Path="D:/Documents/VivadoProjects/PipelineProcessor/PipelineProcessor.xpr">
|
||||||
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||||
|
<Configuration>
|
||||||
|
<Option Name="Id" Val="3fec1083e75e484b88146df78f9d5f01"/>
|
||||||
|
<Option Name="Part" Val="xc7a35tfgg484-1"/>
|
||||||
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||||
|
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||||
|
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||||
|
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||||
|
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||||
|
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||||
|
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||||
|
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||||
|
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||||
|
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||||
|
<Option Name="SimulatorVersionXsim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionModelSim" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionQuesta" Val="2023.2"/>
|
||||||
|
<Option Name="SimulatorVersionXcelium" Val="23.03.002"/>
|
||||||
|
<Option Name="SimulatorVersionVCS" Val="U-2023.03-1"/>
|
||||||
|
<Option Name="SimulatorVersionRiviera" Val="2022.10"/>
|
||||||
|
<Option Name="SimulatorVersionActiveHdl" Val="14.1"/>
|
||||||
|
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||||
|
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||||
|
<Option Name="BoardPart" Val=""/>
|
||||||
|
<Option Name="SourceMgmtMode" Val="DisplayOnly"/>
|
||||||
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||||
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="ProjectType" Val="Default"/>
|
||||||
|
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||||
|
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||||
|
<Option Name="IPCachePermission" Val="read"/>
|
||||||
|
<Option Name="IPCachePermission" Val="write"/>
|
||||||
|
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||||
|
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||||
|
<Option Name="SimCompileState" Val="TRUE"/>
|
||||||
|
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||||
|
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||||
|
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||||
|
<Option Name="EnableBDX" Val="FALSE"/>
|
||||||
|
<Option Name="FeatureSet" Val="FeatureSet_Classic"/>
|
||||||
|
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||||
|
<Option Name="WTXSimExportSim" Val="1"/>
|
||||||
|
<Option Name="WTModelSimExportSim" Val="1"/>
|
||||||
|
<Option Name="WTQuestaExportSim" Val="1"/>
|
||||||
|
<Option Name="WTIesExportSim" Val="0"/>
|
||||||
|
<Option Name="WTVcsExportSim" Val="1"/>
|
||||||
|
<Option Name="WTRivieraExportSim" Val="1"/>
|
||||||
|
<Option Name="WTActivehdlExportSim" Val="1"/>
|
||||||
|
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||||
|
<Option Name="XSimRadix" Val="hex"/>
|
||||||
|
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||||
|
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||||
|
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||||
|
<Option Name="SimTypes" Val="rtl"/>
|
||||||
|
<Option Name="SimTypes" Val="bfm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm"/>
|
||||||
|
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||||
|
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||||
|
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||||
|
<Option Name="ClassicSocBoot" Val="FALSE"/>
|
||||||
|
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||||
|
</Configuration>
|
||||||
|
<FileSets Version="1" Minor="32">
|
||||||
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ALU.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ControlUnit.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/DataMemory.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/Execution.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ExecutionForward.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/HazardUnit.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/ImmediateExtender.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/InstDecode.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/InstFetch.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/InstructionMemory.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/MemoryAccess.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/MemoryForward.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/RegisterFile.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/WriteBack.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<File Path="$PSRCDIR/sources_1/new/CPU.v">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="CPU"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||||
|
<Filter Type="Constrs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="ConstrsType" Val="XDC"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||||
|
<Filter Type="Srcs"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="DesignMode" Val="RTL"/>
|
||||||
|
<Option Name="TopModule" Val="InstFetch"/>
|
||||||
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
<Option Name="TransportPathDelay" Val="0"/>
|
||||||
|
<Option Name="TransportIntDelay" Val="0"/>
|
||||||
|
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||||
|
<Option Name="PamDesignTestbench" Val=""/>
|
||||||
|
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||||
|
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||||
|
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||||
|
<Option Name="SrcSet" Val="sources_1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||||
|
<Filter Type="Utils"/>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
<FileSet Name="phase_locked_loop" Type="BlockSrcs" RelSrcDir="$PSRCDIR/phase_locked_loop" RelGenDir="$PGENDIR/phase_locked_loop">
|
||||||
|
<File Path="$PSRCDIR/sources_1/ip/phase_locked_loop/phase_locked_loop.xci">
|
||||||
|
<FileInfo>
|
||||||
|
<Attr Name="UsedIn" Val="synthesis"/>
|
||||||
|
<Attr Name="UsedIn" Val="implementation"/>
|
||||||
|
<Attr Name="UsedIn" Val="simulation"/>
|
||||||
|
</FileInfo>
|
||||||
|
</File>
|
||||||
|
<Config>
|
||||||
|
<Option Name="TopModule" Val="phase_locked_loop"/>
|
||||||
|
<Option Name="UseBlackboxStub" Val="1"/>
|
||||||
|
</Config>
|
||||||
|
</FileSet>
|
||||||
|
</FileSets>
|
||||||
|
<Simulators>
|
||||||
|
<Simulator Name="XSim">
|
||||||
|
<Option Name="Description" Val="Vivado Simulator"/>
|
||||||
|
<Option Name="CompiledLib" Val="0"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ModelSim">
|
||||||
|
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Questa">
|
||||||
|
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="Riviera">
|
||||||
|
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
<Simulator Name="ActiveHDL">
|
||||||
|
<Option Name="Description" Val="Active-HDL Simulator"/>
|
||||||
|
</Simulator>
|
||||||
|
</Simulators>
|
||||||
|
<Runs Version="1" Minor="21">
|
||||||
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="phase_locked_loop_synth_1" Type="Ft3:Synth" SrcSet="phase_locked_loop" Part="xc7a35tfgg484-1" ConstrsSet="phase_locked_loop" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/phase_locked_loop_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/phase_locked_loop_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/phase_locked_loop_synth_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2023">
|
||||||
|
<Desc>Vivado Synthesis Defaults</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="synth_design"/>
|
||||||
|
</Strategy>
|
||||||
|
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||||
|
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tfgg484-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
<Run Id="phase_locked_loop_impl_1" Type="Ft2:EntireDesign" Part="xc7a35tfgg484-1" ConstrsSet="phase_locked_loop" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="phase_locked_loop_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/phase_locked_loop_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/phase_locked_loop_impl_1">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2023">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2023"/>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles/>
|
||||||
|
</Run>
|
||||||
|
</Runs>
|
||||||
|
<Board/>
|
||||||
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
<Dashboards>
|
||||||
|
<Dashboard Name="default_dashboard">
|
||||||
|
<Gadgets>
|
||||||
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||||
|
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||||
|
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||||
|
</Gadget>
|
||||||
|
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||||
|
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||||
|
</Gadget>
|
||||||
|
</Gadgets>
|
||||||
|
</Dashboard>
|
||||||
|
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||||
|
</Dashboards>
|
||||||
|
</DashboardSummary>
|
||||||
|
</Project>
|
||||||
Reference in New Issue
Block a user